Simulation Results

Simulation Results: i2c

28/07/2026 15:30:25 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.19 %

code
78.19 %

assert
97.46 %

func
79.92 %

line
96.38 %

branch
92.19 %

cond
84.63 %

toggle
73.69 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	23.910s	18523.739us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	4.530s	2672.736us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.650s	140.992us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.630s	36.263us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.050s	569.286us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	0.930s	59.016us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.780s	54.996us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.630s	36.263us	1	1	100.00
	i2c_csr_aliasing	0.930s	59.016us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.710s	35.291us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	16.560s	710.196us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	6.880s	3399.247us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.620s	19.781us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	29.100s	11181.169us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	37.640s	1300.437us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.730s	86.845us	1	1	100.00
	i2c_host_fifo_fmt_empty	7.600s	1891.453us	1	1	100.00
	i2c_host_fifo_reset_rx	3.840s	655.580us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	68.320s	2339.063us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	21.110s	3233.202us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.630s	134.671us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.590s	945.553us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	14.670s	4801.235us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	2.330s	2470.569us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	17.140s	2974.378us	1	1	100.00
	i2c_target_intr_smoke	2.820s	1786.044us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	0.760s	357.694us	1	1	100.00
	i2c_target_fifo_reset_tx	0.720s	103.621us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	912.690s	58786.593us	1	1	100.00
	i2c_target_stress_rd	17.140s	2974.378us	1	1	100.00
	i2c_target_intr_stress_wr	23.930s	5043.718us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	3.840s	5641.224us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	1.120s	803.561us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.070s	1159.552us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	14.250s	10220.175us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.530s	424.121us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.810s	106.262us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	6.880s	3399.247us	1	1	100.00
	i2c_host_perf_precise	1.410s	503.177us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	21.110s	3233.202us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	1.420s	92.837us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	1.820s	1094.715us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.480s	1096.252us	1	1	100.00
	i2c_target_nack_txstretch	0.990s	604.786us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	13.330s	2369.505us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.410s	528.344us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.640s	16.162us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.600s	27.051us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.420s	42.431us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.420s	42.431us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.650s	140.992us	1	1	100.00
	i2c_csr_rw	0.630s	36.263us	1	1	100.00
	i2c_csr_aliasing	0.930s	59.016us	1	1	100.00
	i2c_same_csr_outstanding	0.730s	36.209us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.650s	140.992us	1	1	100.00
	i2c_csr_rw	0.630s	36.263us	1	1	100.00
	i2c_csr_aliasing	0.930s	59.016us	1	1	100.00
	i2c_same_csr_outstanding	0.730s	36.209us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.510s	158.793us	1	1	100.00
	i2c_sec_cm	0.810s	75.376us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.510s	158.793us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	3.020s	308.274us	1
target_error_intr				1
	i2c_target_unexp_stop	0.970s	165.542us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	8.210s	4976.632us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				3 test runs
	i2c_host_error_intr	103320854180930180709329965166061721243941038769818171720778357159996213723832	101	UVM_INFO @ 35290538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	100021196971054181574874191739913217849883654255724074615899775421261633396222	104	UVM_INFO @ 710195606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	88122995307801980983986450380836253086196915472170154621591045072679062994413	101	UVM_INFO @ 4976632333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	63572410248253521470322807433815882277517834544946388870329772566302248096052	89	UVM_INFO @ 945553131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [] vs [*])				1 test run
	i2c_target_unexp_stop	46830951465778363006936186014957511956261736630392202770844911458164191990784	83	UVM_INFO @ 165541747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	110979599440604646209963472416121916705040603012027521147920872418613829425330	84	UVM_INFO @ 10220174740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	8220959717706852852768068827344982748745272816312931043115881294774324068205	103	UVM_INFO @ 308274204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=, Comparison=CompareOpEq, exp_data=, call_count=3)				1 test run
	i2c_host_mode_toggle	1108437762011400389452406545133165048189428848167045756175054762876234285047	84	UVM_INFO @ 134670519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---