Simulation Results: lc_ctrl/volatile_unlock_disabled

 
28/07/2026 15:30:25 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.46 %
  • code
  • 83.70 %
  • assert
  • 94.13 %
  • func
  • 93.55 %
  • line
  • 97.20 %
  • branch
  • 93.70 %
  • cond
  • 79.43 %
  • toggle
  • 85.53 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.150s 187.062us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.780s 21.478us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.720s 54.327us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.190s 398.585us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.880s 94.310us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.720s 50.207us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.720s 54.327us 1 1 100.00
lc_ctrl_csr_aliasing 0.880s 94.310us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.380s 384.839us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.890s 328.498us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.690s 13.908us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.700s 163.724us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.360s 232.331us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 3.580s 3500.785us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.360s 232.331us 1 1 100.00
lc_ctrl_prog_failure 1.700s 163.724us 1 1 100.00
lc_ctrl_errors 3.580s 3500.785us 1 1 100.00
lc_ctrl_security_escalation 4.040s 365.142us 1 1 100.00
lc_ctrl_jtag_state_failure 20.190s 22741.651us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.610s 725.029us 1 1 100.00
lc_ctrl_jtag_errors 19.330s 10071.871us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 1.700s 1457.868us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.060s 2826.294us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.610s 725.029us 1 1 100.00
lc_ctrl_jtag_errors 19.330s 10071.871us 1 1 100.00
lc_ctrl_jtag_access 6.410s 6813.732us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.880s 1200.531us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.140s 1458.616us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.830s 295.631us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 4.900s 3154.927us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.820s 363.139us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.080s 80.333us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.090s 230.078us 1 1 100.00
lc_ctrl_jtag_alert_test 0.870s 47.149us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.510s 7948.784us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.730s 24.373us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 13.720s 2064.267us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.790s 124.818us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.310s 64.964us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.310s 64.964us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.780s 21.478us 1 1 100.00
lc_ctrl_csr_rw 0.720s 54.327us 1 1 100.00
lc_ctrl_csr_aliasing 0.880s 94.310us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.820s 19.299us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.780s 21.478us 1 1 100.00
lc_ctrl_csr_rw 0.720s 54.327us 1 1 100.00
lc_ctrl_csr_aliasing 0.880s 94.310us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.820s 19.299us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.800s 123.798us 1 1 100.00
lc_ctrl_tl_intg_err 1.180s 468.950us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.180s 468.950us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.890s 328.498us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.360s 232.331us 1 1 100.00
lc_ctrl_sec_cm 4.800s 123.798us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.360s 232.331us 1 1 100.00
lc_ctrl_sec_cm 4.800s 123.798us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.360s 232.331us 1 1 100.00
lc_ctrl_sec_cm 4.800s 123.798us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.360s 232.331us 1 1 100.00
lc_ctrl_sec_cm 4.800s 123.798us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.360s 232.331us 1 1 100.00
lc_ctrl_sec_cm 4.800s 123.798us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.360s 232.331us 1 1 100.00
lc_ctrl_sec_cm 4.800s 123.798us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.360s 232.331us 1 1 100.00
lc_ctrl_sec_cm 4.800s 123.798us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.360s 232.331us 1 1 100.00
lc_ctrl_sec_cm 4.800s 123.798us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.040s 365.142us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.380s 384.839us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.060s 2826.294us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.820s 462.993us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.820s 462.993us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 3.780s 1357.386us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.250s 1885.633us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.250s 1885.633us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 13.230s 1079.336us 1 1 100.00