Simulation Results: lc_ctrl/volatile_unlock_enabled

 
28/07/2026 15:30:25 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.59 %
  • code
  • 83.62 %
  • assert
  • 94.97 %
  • func
  • 93.19 %
  • line
  • 97.17 %
  • branch
  • 93.66 %
  • cond
  • 79.61 %
  • toggle
  • 83.16 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 0.890s 87.996us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.730s 17.250us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.740s 47.456us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 0.940s 53.332us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.840s 54.584us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.870s 362.460us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.740s 47.456us 1 1 100.00
lc_ctrl_csr_aliasing 0.840s 54.584us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 1.760s 293.729us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.310s 1086.020us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.660s 35.493us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.110s 18.027us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.050s 1038.045us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 3.200s 828.150us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.050s 1038.045us 1 1 100.00
lc_ctrl_prog_failure 1.110s 18.027us 1 1 100.00
lc_ctrl_errors 3.200s 828.150us 1 1 100.00
lc_ctrl_security_escalation 3.780s 1056.200us 1 1 100.00
lc_ctrl_jtag_state_failure 17.640s 1424.501us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.040s 1580.030us 1 1 100.00
lc_ctrl_jtag_errors 17.870s 2285.547us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.600s 537.828us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.990s 1992.122us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.040s 1580.030us 1 1 100.00
lc_ctrl_jtag_errors 17.870s 2285.547us 1 1 100.00
lc_ctrl_jtag_access 3.640s 469.077us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.910s 2346.074us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.140s 80.660us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.030s 304.799us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.360s 5469.988us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.600s 11841.177us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.020s 42.846us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.830s 345.246us 1 1 100.00
lc_ctrl_jtag_alert_test 0.820s 39.780us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 1.920s 531.076us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.690s 17.062us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 61.570s 25151.187us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.740s 18.191us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.100s 42.572us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.100s 42.572us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.730s 17.250us 1 1 100.00
lc_ctrl_csr_rw 0.740s 47.456us 1 1 100.00
lc_ctrl_csr_aliasing 0.840s 54.584us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.010s 90.677us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.730s 17.250us 1 1 100.00
lc_ctrl_csr_rw 0.740s 47.456us 1 1 100.00
lc_ctrl_csr_aliasing 0.840s 54.584us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.010s 90.677us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.750s 1333.430us 1 1 100.00
lc_ctrl_tl_intg_err 1.840s 278.433us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.840s 278.433us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.310s 1086.020us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.050s 1038.045us 1 1 100.00
lc_ctrl_sec_cm 5.750s 1333.430us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.050s 1038.045us 1 1 100.00
lc_ctrl_sec_cm 5.750s 1333.430us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.050s 1038.045us 1 1 100.00
lc_ctrl_sec_cm 5.750s 1333.430us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.050s 1038.045us 1 1 100.00
lc_ctrl_sec_cm 5.750s 1333.430us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.050s 1038.045us 1 1 100.00
lc_ctrl_sec_cm 5.750s 1333.430us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.050s 1038.045us 1 1 100.00
lc_ctrl_sec_cm 5.750s 1333.430us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.050s 1038.045us 1 1 100.00
lc_ctrl_sec_cm 5.750s 1333.430us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.050s 1038.045us 1 1 100.00
lc_ctrl_sec_cm 5.750s 1333.430us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.780s 1056.200us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 1.760s 293.729us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.990s 1992.122us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.320s 457.716us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.320s 457.716us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 3.930s 1378.916us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.700s 507.145us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.700s 507.145us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 4.080s 2285.112us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 14328504281501500034523011862847843752991488300184666854917224496395174811962 159
UVM_INFO @ 2285112303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---