Simulation Results: otbn

 
28/07/2026 15:30:25 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.27 %
  • code
  • 86.25 %
  • assert
  • 90.10 %
  • func
  • 97.46 %
  • block
  • 99.28 %
  • line
  • 99.47 %
  • branch
  • 94.82 %
  • toggle
  • 84.53 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 17.000s 369.663us 1 1 100.00
single_binary 1 1 100.00
otbn_single 13.000s 26.974us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 35.000s 27.157us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 34.000s 177.811us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 36.000s 106.645us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 35.000s 70.258us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 37.000s 170.767us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 34.000s 177.811us 1 1 100.00
otbn_csr_aliasing 35.000s 70.258us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 58.000s 1435.777us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 55.000s 1220.692us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 34.000s 742.558us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 63.000s 337.658us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 70.000s 291.403us 1 1 100.00
stress_all 0 1 0.00
otbn_stress_all 43.000s 153.915us 0 1 0.00
lc_escalation 1 1 100.00
otbn_escalate 57.000s 404.773us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 4.000s 28.500us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 10.000s 67.736us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 36.000s 15.344us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 27.000s 15.336us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 4.000s 148.367us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 4.000s 148.367us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 35.000s 27.157us 1 1 100.00
otbn_csr_rw 34.000s 177.811us 1 1 100.00
otbn_csr_aliasing 35.000s 70.258us 1 1 100.00
otbn_same_csr_outstanding 12.000s 47.468us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 35.000s 27.157us 1 1 100.00
otbn_csr_rw 34.000s 177.811us 1 1 100.00
otbn_csr_aliasing 35.000s 70.258us 1 1 100.00
otbn_same_csr_outstanding 12.000s 47.468us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 33.000s 40.804us 1 1 100.00
otbn_dmem_err 34.000s 13.277us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 39.000s 55.332us 1 1 100.00
otbn_controller_ispr_rdata_err 39.000s 57.160us 1 1 100.00
otbn_mac_bignum_acc_err 30.000s 101.799us 1 1 100.00
otbn_urnd_err 7.000s 20.955us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 31.000s 34.369us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 25.000s 43.676us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 18.000s 57.896us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 132.000s 856.051us 1 1 100.00
otbn_tl_intg_err 9.000s 277.411us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 31.000s 373.235us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 132.000s 856.051us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 132.000s 856.051us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 17.000s 369.663us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 34.000s 13.277us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 33.000s 40.804us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 9.000s 277.411us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 57.000s 404.773us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 33.000s 40.804us 1 1 100.00
otbn_dmem_err 34.000s 13.277us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 28.500us 1 1 100.00
otbn_illegal_mem_acc 31.000s 34.369us 1 1 100.00
otbn_sec_cm 132.000s 856.051us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 132.000s 856.051us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 13.000s 26.974us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 33.000s 40.804us 1 1 100.00
otbn_dmem_err 34.000s 13.277us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 28.500us 1 1 100.00
otbn_illegal_mem_acc 31.000s 34.369us 1 1 100.00
otbn_sec_cm 132.000s 856.051us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 132.000s 856.051us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 57.000s 404.773us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 33.000s 40.804us 1 1 100.00
otbn_dmem_err 34.000s 13.277us 1 1 100.00
otbn_zero_state_err_urnd 4.000s 28.500us 1 1 100.00
otbn_illegal_mem_acc 31.000s 34.369us 1 1 100.00
otbn_sec_cm 132.000s 856.051us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 132.000s 856.051us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 13.000s 26.974us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 35.000s 99.883us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 15.000s 41.158us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 41.000s 604.887us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 41.000s 604.887us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 17.000s 141.691us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 132.000s 856.051us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 132.000s 856.051us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 17.000s 121.295us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 132.000s 856.051us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 132.000s 856.051us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 10.000s 107.516us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 10.000s 107.516us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 10.000s 55.596us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 13.000s 26.974us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 13.000s 26.974us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 13.000s 26.974us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 70.000s 291.403us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 13.000s 26.974us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 13.000s 26.974us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 8.000s 161.998us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 13.000s 26.974us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 132.000s 856.051us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 227.000s 5421.114us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 12.000s 56.903us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_otbn_*/rtl/otbn_rnd.sv,233): Assertion UrndNoReseedOnReset_A has failed 1 test run
otbn_stress_all 88671793392436801607600565116879571665799741549260521839767650807677948486047 259
UVM_ERROR @ 153915111 ps: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 153915111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---