Simulation Results: otp_ctrl

 
28/07/2026 15:30:25 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.09 %
  • code
  • 76.53 %
  • assert
  • 94.64 %
  • func
  • 72.11 %
  • line
  • 88.53 %
  • branch
  • 83.55 %
  • cond
  • 90.21 %
  • toggle
  • 76.10 %
  • FSM
  • 44.27 %
Validation stages
V1
100.00%
V2
95.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.260s 58.696us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 3.610s 388.031us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.670s 121.461us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.510s 585.597us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 7.270s 1154.016us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.000s 77.267us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.880s 277.116us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.510s 585.597us 1 1 100.00
otp_ctrl_csr_aliasing 3.000s 77.267us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.090s 93.182us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.150s 143.989us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 11.340s 1505.348us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.020s 444.841us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 12.450s 1297.340us 1 1 100.00
otp_ctrl_check_fail 7.870s 611.681us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 3.720s 181.283us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 8.270s 2704.296us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 12.800s 2059.404us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 12.600s 3512.615us 1 1 100.00
otp_ctrl_parallel_lc_esc 6.630s 3587.309us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 11.040s 364.451us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 1.350s 92.427us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 4.020s 626.761us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 14.980s 4800.148us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.110s 58.054us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.510s 99.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.430s 223.959us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.430s 223.959us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.670s 121.461us 1 1 100.00
otp_ctrl_csr_rw 1.510s 585.597us 1 1 100.00
otp_ctrl_csr_aliasing 3.000s 77.267us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.430s 1297.108us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.670s 121.461us 1 1 100.00
otp_ctrl_csr_rw 1.510s 585.597us 1 1 100.00
otp_ctrl_csr_aliasing 3.000s 77.267us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.430s 1297.108us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
otp_ctrl_tl_intg_err 12.250s 4884.673us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 12.250s 4884.673us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 3.610s 388.031us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 3.610s 388.031us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.630s 3587.309us 1 1 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.630s 3587.309us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.630s 3587.309us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.630s 3587.309us 1 1 100.00
otp_ctrl_macro_errs 1.350s 92.427us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.630s 3587.309us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.630s 3587.309us 1 1 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.630s 3587.309us 1 1 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.630s 3587.309us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.630s 3587.309us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.630s 3587.309us 1 1 100.00
otp_ctrl_macro_errs 1.350s 92.427us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.630s 3587.309us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.630s 3587.309us 1 1 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.020s 444.841us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 7.870s 611.681us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 8.270s 2704.296us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 8.270s 2704.296us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 8.270s 2704.296us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 8.270s 2704.296us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 8.270s 2704.296us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 3.610s 388.031us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 8.270s 2704.296us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 3.610s 388.031us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 98.010s 11633.886us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 3.720s 181.283us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 3.610s 388.031us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 3.610s 388.031us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 1.350s 92.427us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 9.260s 7875.655us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 6.640s 365.690us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1208) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 111968686591417590556559822860637968294173702074986967644338881907994525273880 402
UVM_INFO @ 92427041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1208) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_stress_all_with_rand_reset 106952217370188420794814650417601651435848499710582706484999810948675125554361 2312
UVM_INFO @ 365690389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---