Simulation Results: pwrmgr

 
28/07/2026 15:30:25 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.03 %
  • code
  • 97.48 %
  • assert
  • 98.43 %
  • func
  • 98.19 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 96.32 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.570s 44.154us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.650s 32.038us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.600s 47.282us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.440s 346.699us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.780s 87.758us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.040s 48.324us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.600s 47.282us 1 1 100.00
pwrmgr_csr_aliasing 0.780s 87.758us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.670s 84.756us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.670s 84.756us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.620s 33.964us 1 1 100.00
pwrmgr_lowpower_invalid 0.630s 45.601us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.740s 69.711us 1 1 100.00
pwrmgr_reset_invalid 0.680s 158.152us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.740s 69.711us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.600s 129.130us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.710s 86.287us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.830s 202.817us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 0.700s 153.979us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.600s 19.787us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.330s 70.382us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.330s 70.382us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.650s 32.038us 1 1 100.00
pwrmgr_csr_rw 0.600s 47.282us 1 1 100.00
pwrmgr_csr_aliasing 0.780s 87.758us 1 1 100.00
pwrmgr_same_csr_outstanding 0.650s 75.469us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.650s 32.038us 1 1 100.00
pwrmgr_csr_rw 0.600s 47.282us 1 1 100.00
pwrmgr_csr_aliasing 0.780s 87.758us 1 1 100.00
pwrmgr_same_csr_outstanding 0.650s 75.469us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 0.900s 155.740us 1 1 100.00
pwrmgr_sec_cm 1.070s 852.137us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.070s 852.137us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.070s 852.137us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 0.900s 155.740us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.760s 797.160us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.600s 129.130us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.720s 705.098us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.780s 72.925us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.600s 29.613us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.070s 852.137us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.070s 852.137us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.070s 852.137us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.580s 41.453us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.590s 61.789us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.640s 50.043us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.600s 47.282us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.600s 47.282us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.660s 797.998us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 3.890s 1427.883us 1 1 100.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 75521712519956719706576873685047237189981953614380171699757963704201800661783 84
UVM_ERROR @ 797998072 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 797998072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---