Simulation Results: spi_host

 
28/07/2026 15:30:25 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.13 %
  • code
  • 95.03 %
  • assert
  • 95.27 %
  • func
  • 89.08 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 24.000s 5562.825us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 24.106us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 111.058us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 79.799us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 151.172us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 41.624us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 111.058us 1 1 100.00
spi_host_csr_aliasing 1.000s 151.172us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 42.374us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 28.356us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 19.647us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 255.392us 1 1 100.00
spi_host_error_cmd 1.000s 20.247us 1 1 100.00
spi_host_event 4.000s 992.949us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 83.203us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 83.203us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 83.203us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 253.000s 12202.403us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 2.000s 73.996us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 41.655us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 83.203us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 83.203us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 24.000s 5562.825us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 24.000s 5562.825us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 2.000s 189.661us 1 1 100.00
spien 1 1 100.00
spi_host_spien 2.000s 906.045us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 22.000s 3856.667us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 191.478us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 255.392us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 36.573us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 2.000s 136.015us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 454.755us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 454.755us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 24.106us 1 1 100.00
spi_host_csr_rw 1.000s 111.058us 1 1 100.00
spi_host_csr_aliasing 1.000s 151.172us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 56.987us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 24.106us 1 1 100.00
spi_host_csr_rw 1.000s 111.058us 1 1 100.00
spi_host_csr_aliasing 1.000s 151.172us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 56.987us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 104.364us 1 1 100.00
spi_host_sec_cm 1.000s 44.861us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 104.364us 1 1 100.00