Simulation Results: sram_ctrl/main

 
28/07/2026 15:30:25 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.36 %
  • code
  • 95.75 %
  • assert
  • 97.14 %
  • func
  • 93.20 %
  • block
  • 96.16 %
  • line
  • 96.82 %
  • branch
  • 94.32 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 682.485us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 30.643us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 56.945us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 61.545us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.830us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 3918.013us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 56.945us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.830us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 194.000s 45385.456us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 84.000s 20156.466us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 17.000s 9070.808us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 91.000s 6713.661us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 104.000s 7361.182us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 39.000s 32028.054us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 15.000s 20819.446us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 31.000s 34471.499us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 2781.429us 1 1 100.00
sram_ctrl_partial_access_b2b 134.000s 24078.147us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 4.000s 2667.916us 0 1 0.00
sram_ctrl_throughput_w_partial_write 3.000s 679.420us 0 1 0.00
sram_ctrl_throughput_w_readback 3.000s 681.187us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 7.000s 764.671us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 1023.440us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 35.000s 13888.152us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 20.423us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 94.373us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 94.373us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 30.643us 1 1 100.00
sram_ctrl_csr_rw 1.000s 56.945us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.830us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 42.318us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 30.643us 1 1 100.00
sram_ctrl_csr_rw 1.000s 56.945us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 18.830us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 42.318us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 11.000s 26461.137us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 1188.367us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 419.606us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 1188.367us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 419.606us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 764.671us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 764.671us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 56.945us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 31.000s 34471.499us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 31.000s 34471.499us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 31.000s 34471.499us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 15.000s 20819.446us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 2658.565us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 11.000s 26461.137us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.000s 1723.981us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 682.485us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 682.485us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 31.000s 34471.499us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 1188.367us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 15.000s 20819.446us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 1188.367us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1188.367us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 682.485us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1188.367us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 12.000s 1056.432us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 90650867709873943263467055966736141203315924302394572589456200340706719935823 86
UVM_INFO @ 2667916413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 43755458135184650817576464889582805552327066528383633445929053167640496237033 86
UVM_INFO @ 679420417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 74499171616970531459746655208943981390292707310880874517467496145312169421587 86
UVM_INFO @ 681187214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---