Simulation Results: sram_ctrl/ret

 
28/07/2026 15:30:25 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.48 %
  • code
  • 82.11 %
  • assert
  • 97.94 %
  • func
  • 94.40 %
  • block
  • 93.47 %
  • line
  • 94.61 %
  • branch
  • 88.85 %
  • toggle
  • 78.32 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 205.111us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 68.894us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 46.950us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 472.768us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 33.898us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 116.427us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 46.950us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 33.898us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.000s 1700.170us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 2.000s 51.605us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 6.000s 331.665us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 164.000s 8010.364us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 6.000s 2004.310us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 4.000s 656.799us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 4.000s 3269.561us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 9.000s 5251.650us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 45.938us 1 1 100.00
sram_ctrl_partial_access_b2b 215.000s 70118.493us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 1.000s 27.435us 0 1 0.00
sram_ctrl_throughput_w_partial_write 1.000s 67.408us 0 1 0.00
sram_ctrl_throughput_w_readback 1.000s 21.988us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 4.000s 1459.784us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 72.438us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 23.000s 4498.579us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 21.386us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 28.441us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 28.441us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 68.894us 1 1 100.00
sram_ctrl_csr_rw 1.000s 46.950us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 33.898us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 23.848us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 68.894us 1 1 100.00
sram_ctrl_csr_rw 1.000s 46.950us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 33.898us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 23.848us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 444.737us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 2649.583us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 753.408us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 2649.583us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 753.408us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 4.000s 1459.784us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 4.000s 1459.784us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 46.950us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 9.000s 5251.650us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 5251.650us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 5251.650us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 4.000s 3269.561us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 250.282us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 444.737us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 39.309us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 205.111us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 205.111us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 9.000s 5251.650us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 2649.583us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 4.000s 3269.561us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 2649.583us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 2649.583us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 205.111us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 2649.583us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 21.000s 1455.800us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 9215853413931677690698766263010229253674808305635777173642339900194248982434 86
UVM_INFO @ 27434789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 20086582587908395828690666797969123954094358468486685332104920279941312237192 86
UVM_INFO @ 67408339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 44731286049216031912332026140361404527718925657195847062667924936399336981452 86
UVM_INFO @ 21987962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---