Simulation Results: sysrst_ctrl

 
28/07/2026 15:30:25 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.50 %
  • code
  • 92.82 %
  • assert
  • 94.25 %
  • func
  • 69.43 %
  • line
  • 97.28 %
  • branch
  • 97.29 %
  • cond
  • 95.18 %
  • toggle
  • 100.00 %
  • FSM
  • 74.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.330s 2131.050us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 1.500s 2495.964us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.240s 2263.307us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.500s 2295.127us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 9.320s 6038.284us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 3.810s 2036.963us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 35.620s 76429.434us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 5.040s 2414.336us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.710s 2058.261us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 3.810s 2036.963us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.040s 2414.336us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 54.970s 77772.627us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 62.740s 162198.382us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 5.710s 3734.396us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 3.810s 2476.270us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 4.430s 2513.209us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.000s 2164.585us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.400s 2628.079us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 3.630s 2617.445us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 2.230s 8810.129us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 13.750s 36352.088us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 20.310s 13586.387us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 3.490s 2014.385us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 0.830s 2104.899us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 3.140s 2081.600us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 3.140s 2081.600us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 9.320s 6038.284us 1 1 100.00
sysrst_ctrl_csr_rw 3.810s 2036.963us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.040s 2414.336us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 7.460s 4408.082us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 9.320s 6038.284us 1 1 100.00
sysrst_ctrl_csr_rw 3.810s 2036.963us 1 1 100.00
sysrst_ctrl_csr_aliasing 5.040s 2414.336us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 7.460s 4408.082us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 15.790s 42189.167us 1 1 100.00
sysrst_ctrl_tl_intg_err 19.200s 42529.538us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 19.200s 42529.538us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 5.180s 2778.216us 1 1 100.00