Simulation Results: uart

 
28/07/2026 15:30:25 DVSim: v1.50.0 sha: c01a435 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.56 %
  • code
  • 91.22 %
  • assert
  • 98.56 %
  • func
  • 51.89 %
  • line
  • 99.17 %
  • branch
  • 96.97 %
  • cond
  • 94.63 %
  • toggle
  • 74.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 2.040s 690.938us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.560s 51.624us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.600s 86.129us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.180s 142.620us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.700s 156.175us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.620s 30.225us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.600s 86.129us 1 1 100.00
uart_csr_aliasing 0.700s 156.175us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 64.170s 128089.354us 1 1 100.00
parity 2 2 100.00
uart_smoke 2.040s 690.938us 1 1 100.00
uart_tx_rx 64.170s 128089.354us 1 1 100.00
parity_error 2 2 100.00
uart_intr 4.880s 17644.027us 1 1 100.00
uart_rx_parity_err 71.860s 91543.611us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 64.170s 128089.354us 1 1 100.00
uart_intr 4.880s 17644.027us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 31.200s 45161.920us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 16.780s 24261.666us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 45.670s 58949.684us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 4.880s 17644.027us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 4.880s 17644.027us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 4.880s 17644.027us 1 1 100.00
perf 1 1 100.00
uart_perf 30.850s 5155.130us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 5.710s 5263.411us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 5.710s 5263.411us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 7.100s 18612.123us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 1.340s 5576.809us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 8.860s 6291.584us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 3.300s 3813.463us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 112.190s 253190.435us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 152.010s 157885.924us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.570s 30.039us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.570s 44.723us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.590s 432.003us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.590s 432.003us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.560s 51.624us 1 1 100.00
uart_csr_rw 0.600s 86.129us 1 1 100.00
uart_csr_aliasing 0.700s 156.175us 1 1 100.00
uart_same_csr_outstanding 0.650s 270.254us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.560s 51.624us 1 1 100.00
uart_csr_rw 0.600s 86.129us 1 1 100.00
uart_csr_aliasing 0.700s 156.175us 1 1 100.00
uart_same_csr_outstanding 0.650s 270.254us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.670s 369.935us 1 1 100.00
uart_tl_intg_err 1.080s 267.994us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.080s 267.994us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 20.060s 3075.192us 1 1 100.00