Simulation Results: adc_ctrl

 
29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 66.82 %
  • code
  • 94.83 %
  • assert
  • 92.54 %
  • func
  • 13.09 %
  • line
  • 98.62 %
  • branch
  • 97.09 %
  • cond
  • 86.81 %
  • toggle
  • 99.76 %
  • FSM
  • 91.89 %
Validation stages
V1
100.00%
V2
57.89%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 1.980s 5776.891us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 0.870s 683.637us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.820s 455.532us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 28.040s 26329.324us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.920s 589.539us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.900s 508.973us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.820s 455.532us 1 1 100.00
adc_ctrl_csr_aliasing 1.920s 589.539us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 0.920s 280.200us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.930s 478.888us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.690s 369.129us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.790s 405.059us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.820s 430.587us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.940s 377.818us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.740s 399.534us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.740s 508.116us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 1.770s 3107.792us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 56.940s 44602.230us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 53.290s 118797.310us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 40.910s 33624.734us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.780s 453.815us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.120s 397.536us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.130s 1046.651us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.130s 1046.651us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.870s 683.637us 1 1 100.00
adc_ctrl_csr_rw 0.820s 455.532us 1 1 100.00
adc_ctrl_csr_aliasing 1.920s 589.539us 1 1 100.00
adc_ctrl_same_csr_outstanding 4.290s 4972.163us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.870s 683.637us 1 1 100.00
adc_ctrl_csr_rw 0.820s 455.532us 1 1 100.00
adc_ctrl_csr_aliasing 1.920s 589.539us 1 1 100.00
adc_ctrl_same_csr_outstanding 4.290s 4972.163us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 1.040s 4405.050us 1 1 100.00
adc_ctrl_tl_intg_err 6.560s 8751.459us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 6.560s 8751.459us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 2.930s 1790.170us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 9 test runs
adc_ctrl_filters_polled 87474320393513601483609532417909814337348575562479477907422048020029468845754 386
UVM_INFO @ 280200130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 48270542937254118418247135944184632404852719500979899555945348211550739911296 386
UVM_INFO @ 478888170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 6730739102983515148444693209678418914961083095643481806055974365600509101628 386
UVM_INFO @ 369128729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 100292422251364073729156072828083521539308693938886669501242825136325622836014 386
UVM_INFO @ 405058631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 19807390850356518662872084028638641119623747612197641216619185421246229058690 386
UVM_INFO @ 430586725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 69703652208665773351112924500318566156450652689515209523695591027549997733476 386
UVM_INFO @ 377817606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 40634927868151438197415061507113440459511142902069906117723616431906339336266 386
UVM_INFO @ 508115625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 103714649018396862705431659811543012557681796764484815659360648169266782674534 386
UVM_INFO @ 399533931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 26261214040304429501337391922162283236899243643040781031529791786781313709074 423
UVM_INFO @ 1790169648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---