Simulation Results: aes/masked

 
29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.70 %
  • code
  • 94.08 %
  • assert
  • 98.23 %
  • func
  • 73.80 %
  • block
  • 94.15 %
  • line
  • 95.77 %
  • branch
  • 86.99 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
94.12%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 64.693us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 164.591us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 80.177us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 119.112us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 8.000s 4404.487us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 150.783us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 106.955us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 119.112us 1 1 100.00
aes_csr_aliasing 2.000s 150.783us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 164.591us 1 1 100.00
aes_config_error 2.000s 267.424us 1 1 100.00
aes_stress 5.000s 172.354us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 164.591us 1 1 100.00
aes_config_error 2.000s 267.424us 1 1 100.00
aes_stress 5.000s 172.354us 1 1 100.00
back2back 2 2 100.00
aes_stress 5.000s 172.354us 1 1 100.00
aes_b2b 10.000s 806.948us 1 1 100.00
backpressure 1 1 100.00
aes_stress 5.000s 172.354us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 164.591us 1 1 100.00
aes_config_error 2.000s 267.424us 1 1 100.00
aes_stress 5.000s 172.354us 1 1 100.00
aes_alert_reset 5.000s 646.718us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 60.860us 1 1 100.00
aes_config_error 2.000s 267.424us 1 1 100.00
aes_alert_reset 5.000s 646.718us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 70.979us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 9.000s 2558.289us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 5.000s 646.718us 1 1 100.00
stress 1 1 100.00
aes_stress 5.000s 172.354us 1 1 100.00
sideload 2 2 100.00
aes_stress 5.000s 172.354us 1 1 100.00
aes_sideload 7.000s 68.513us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 161.402us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 27.000s 2212.782us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 60.004us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 595.068us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 595.068us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 80.177us 1 1 100.00
aes_csr_rw 2.000s 119.112us 1 1 100.00
aes_csr_aliasing 2.000s 150.783us 1 1 100.00
aes_same_csr_outstanding 2.000s 68.417us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 80.177us 1 1 100.00
aes_csr_rw 2.000s 119.112us 1 1 100.00
aes_csr_aliasing 2.000s 150.783us 1 1 100.00
aes_same_csr_outstanding 2.000s 68.417us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 6.000s 1661.637us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 4.000s 1107.550us 0 1 0.00
aes_control_fi 25.000s 10112.261us 0 1 0.00
aes_cipher_fi 2.000s 65.670us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 62.786us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 62.786us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 62.786us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 62.786us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 299.430us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 8.000s 1315.179us 1 1 100.00
aes_tl_intg_err 2.000s 221.283us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 221.283us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 5.000s 646.718us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 62.786us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 62.786us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 164.591us 1 1 100.00
aes_stress 5.000s 172.354us 1 1 100.00
aes_alert_reset 5.000s 646.718us 1 1 100.00
aes_core_fi 2.000s 101.726us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 267.424us 1 1 100.00
aes_stress 5.000s 172.354us 1 1 100.00
aes_core_fi 2.000s 101.726us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 62.786us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 3.000s 70.728us 1 1 100.00
aes_stress 5.000s 172.354us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 5.000s 172.354us 1 1 100.00
aes_sideload 7.000s 68.513us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 3.000s 70.728us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 3.000s 70.728us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 3.000s 70.728us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 3.000s 70.728us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 3.000s 70.728us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 5.000s 172.354us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 5.000s 172.354us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 4.000s 1107.550us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 4.000s 1107.550us 0 1 0.00
aes_control_fi 25.000s 10112.261us 0 1 0.00
aes_cipher_fi 2.000s 65.670us 1 1 100.00
aes_ctr_fi 2.000s 62.759us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 4.000s 1107.550us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 4.000s 1107.550us 0 1 0.00
aes_control_fi 25.000s 10112.261us 0 1 0.00
aes_cipher_fi 2.000s 65.670us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 65.670us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 4.000s 1107.550us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 4.000s 1107.550us 0 1 0.00
aes_control_fi 25.000s 10112.261us 0 1 0.00
aes_ctr_fi 2.000s 62.759us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 4.000s 1107.550us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 4.000s 1107.550us 0 1 0.00
aes_control_fi 25.000s 10112.261us 0 1 0.00
aes_cipher_fi 2.000s 65.670us 1 1 100.00
aes_ctr_fi 2.000s 62.759us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 5.000s 646.718us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 4.000s 1107.550us 0 1 0.00
aes_control_fi 25.000s 10112.261us 0 1 0.00
aes_cipher_fi 2.000s 65.670us 1 1 100.00
aes_ctr_fi 2.000s 62.759us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 4.000s 1107.550us 0 1 0.00
aes_control_fi 25.000s 10112.261us 0 1 0.00
aes_cipher_fi 2.000s 65.670us 1 1 100.00
aes_ctr_fi 2.000s 62.759us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 4.000s 1107.550us 0 1 0.00
aes_control_fi 25.000s 10112.261us 0 1 0.00
aes_ctr_fi 2.000s 62.759us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 4.000s 1107.550us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 4.000s 1107.550us 0 1 0.00
aes_control_fi 25.000s 10112.261us 0 1 0.00
aes_cipher_fi 2.000s 65.670us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 16.000s 1408.344us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_stress_all 4207755326949993856160069764413771294697885113608684588168357570018390716319 88318
UVM_INFO @ 2212781904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 33074948163137248723601577429937671377750249556761288795901467234493491424403 370
UVM_INFO @ 1408344200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 48875792596289119031432574792111775960254958851114144765502360208596147875214 5915
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 5
----| Seen: 4
----| Expected corrupted: 0
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 1 test run
aes_control_fi 15922621962403605189668972179972927236680927532313875385837313924380921166027 149
UVM_INFO @ 10112261002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---