Simulation Results: aes/unmasked

 
29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.81 %
  • code
  • 90.63 %
  • assert
  • 97.73 %
  • func
  • 72.08 %
  • block
  • 91.01 %
  • line
  • 92.66 %
  • branch
  • 82.98 %
  • toggle
  • 97.99 %
  • FSM
  • 88.89 %
Validation stages
V1
100.00%
V2
94.12%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 66.237us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 522.874us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 113.020us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 97.343us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 255.411us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 99.255us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 61.157us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 97.343us 1 1 100.00
aes_csr_aliasing 2.000s 99.255us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 522.874us 1 1 100.00
aes_config_error 2.000s 135.762us 1 1 100.00
aes_stress 2.000s 84.650us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 522.874us 1 1 100.00
aes_config_error 2.000s 135.762us 1 1 100.00
aes_stress 2.000s 84.650us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 84.650us 1 1 100.00
aes_b2b 2.000s 97.375us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 84.650us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 522.874us 1 1 100.00
aes_config_error 2.000s 135.762us 1 1 100.00
aes_stress 2.000s 84.650us 1 1 100.00
aes_alert_reset 1.000s 144.743us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 171.240us 1 1 100.00
aes_config_error 2.000s 135.762us 1 1 100.00
aes_alert_reset 1.000s 144.743us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 196.668us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 3.000s 278.135us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 1.000s 144.743us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 84.650us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 84.650us 1 1 100.00
aes_sideload 2.000s 96.550us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 82.169us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 10.000s 144.136us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 1.000s 91.458us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 100.215us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 100.215us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 113.020us 1 1 100.00
aes_csr_rw 2.000s 97.343us 1 1 100.00
aes_csr_aliasing 2.000s 99.255us 1 1 100.00
aes_same_csr_outstanding 2.000s 108.426us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 113.020us 1 1 100.00
aes_csr_rw 2.000s 97.343us 1 1 100.00
aes_csr_aliasing 2.000s 99.255us 1 1 100.00
aes_same_csr_outstanding 2.000s 108.426us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 2.000s 29.562us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 2.000s 103.566us 0 1 0.00
aes_control_fi 1.000s 66.800us 1 1 100.00
aes_cipher_fi 2.000s 108.138us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 98.994us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 98.994us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 98.994us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 98.994us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 278.358us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 5.000s 1713.702us 1 1 100.00
aes_tl_intg_err 2.000s 579.601us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 579.601us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 1.000s 144.743us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 98.994us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 98.994us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 522.874us 1 1 100.00
aes_stress 2.000s 84.650us 1 1 100.00
aes_alert_reset 1.000s 144.743us 1 1 100.00
aes_core_fi 2.000s 82.594us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 135.762us 1 1 100.00
aes_stress 2.000s 84.650us 1 1 100.00
aes_core_fi 2.000s 82.594us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 98.994us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 127.997us 1 1 100.00
aes_stress 2.000s 84.650us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 84.650us 1 1 100.00
aes_sideload 2.000s 96.550us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 127.997us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 127.997us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 127.997us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 127.997us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 127.997us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 84.650us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 84.650us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 103.566us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 103.566us 0 1 0.00
aes_control_fi 1.000s 66.800us 1 1 100.00
aes_cipher_fi 2.000s 108.138us 1 1 100.00
aes_ctr_fi 1.000s 50.948us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 103.566us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 103.566us 0 1 0.00
aes_control_fi 1.000s 66.800us 1 1 100.00
aes_cipher_fi 2.000s 108.138us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 108.138us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 103.566us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 103.566us 0 1 0.00
aes_control_fi 1.000s 66.800us 1 1 100.00
aes_ctr_fi 1.000s 50.948us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 103.566us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 103.566us 0 1 0.00
aes_control_fi 1.000s 66.800us 1 1 100.00
aes_cipher_fi 2.000s 108.138us 1 1 100.00
aes_ctr_fi 1.000s 50.948us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 1.000s 144.743us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 103.566us 0 1 0.00
aes_control_fi 1.000s 66.800us 1 1 100.00
aes_cipher_fi 2.000s 108.138us 1 1 100.00
aes_ctr_fi 1.000s 50.948us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 103.566us 0 1 0.00
aes_control_fi 1.000s 66.800us 1 1 100.00
aes_cipher_fi 2.000s 108.138us 1 1 100.00
aes_ctr_fi 1.000s 50.948us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 103.566us 0 1 0.00
aes_control_fi 1.000s 66.800us 1 1 100.00
aes_ctr_fi 1.000s 50.948us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 103.566us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 103.566us 0 1 0.00
aes_control_fi 1.000s 66.800us 1 1 100.00
aes_cipher_fi 2.000s 108.138us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 10.000s 587.868us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 2 test runs
aes_reseed 58206512746779532161302482067291731660680560544702398146974872092107087741322 1913
UVM_INFO @ 29562125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 96600550810809496349333779046453826261021085713890522239302309898974014779688 19499
UVM_INFO @ 144136262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 45849155830303484724129656148475136029895634874154079202036019634055263349064 5243
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 6
----| Seen: 1
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 21092162231135523813193907218878621589819891047963569688505683388197503848962 553
UVM_INFO @ 587867502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---