Simulation Results: alert_handler

 
29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.69 %
  • code
  • 90.60 %
  • assert
  • 98.13 %
  • func
  • 77.33 %
  • line
  • 99.69 %
  • branch
  • 97.87 %
  • cond
  • 90.81 %
  • toggle
  • 88.82 %
  • FSM
  • 75.81 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 11.170s 514.105us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 3.450s 209.983us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 5.750s 537.703us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 154.210s 18992.411us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 36.230s 2158.408us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 3.390s 34.079us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 5.750s 537.703us 1 1 100.00
alert_handler_csr_aliasing 36.230s 2158.408us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 47.810s 5157.171us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 41.920s 11177.226us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 484.170s 94172.057us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 6.020s 80.023us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 11.170s 514.105us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 32.210s 3127.337us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 10.040s 1411.596us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 172.380s 8478.195us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 1095.400s 36786.794us 1 1 100.00
alert_handler_lpg_stub_clk 1453.820s 193522.022us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 887.040s 69161.784us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 4.250s 109.882us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.200s 25.383us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.170s 8.483us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 5.600s 250.558us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 5.600s 250.558us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 3.450s 209.983us 1 1 100.00
alert_handler_csr_rw 5.750s 537.703us 1 1 100.00
alert_handler_csr_aliasing 36.230s 2158.408us 1 1 100.00
alert_handler_same_csr_outstanding 13.790s 318.972us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 3.450s 209.983us 1 1 100.00
alert_handler_csr_rw 5.750s 537.703us 1 1 100.00
alert_handler_csr_aliasing 36.230s 2158.408us 1 1 100.00
alert_handler_same_csr_outstanding 13.790s 318.972us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 52.690s 1667.267us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 52.690s 1667.267us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 52.690s 1667.267us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 52.690s 1667.267us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 172.300s 2200.973us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 18.100s 936.637us 1 1 100.00
alert_handler_tl_intg_err 28.520s 5771.201us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 28.520s 5771.201us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 52.690s 1667.267us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 11.170s 514.105us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 11.170s 514.105us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 11.170s 514.105us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 11.170s 514.105us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 6.020s 80.023us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1095.400s 36786.794us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 6.020s 80.023us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 484.170s 94172.057us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 484.170s 94172.057us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 18.100s 936.637us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 18.100s 936.637us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 18.100s 936.637us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 18.100s 936.637us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 18.100s 936.637us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 18.100s 936.637us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 18.100s 936.637us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 18.100s 936.637us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 18.100s 936.637us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 29.690s 764.978us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 52189758581075321737546490108917503784395837605905498093907590905483872538032 196
UVM_INFO @ 109882306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 23814459581767046602094992226896439507046979755611240399383315380521519945374 84
UVM_INFO @ 764978017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---