Simulation Results

Simulation Results: chip

29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
72.33 %

code
81.39 %

assert
97.37 %

func
38.24 %

line
94.23 %

branch
93.66 %

cond
88.71 %

toggle
73.22 %

FSM
57.14 %

Validation stages

V1		100.00%
V2		76.17%
V2S		100.00%
V3		61.54%
unmapped		63.64%

18/18 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	188.130s	2887.795us	1	1	100.00
	chip_sw_example_rom	90.990s	3617.046us	1	1	100.00
	chip_sw_example_manufacturer	224.520s	4349.517us	1	1	100.00
	chip_sw_example_concurrency	172.800s	2881.781us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	151.190s	4547.310us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	174.310s	4371.771us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	3235.990s	44349.146us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	4389.260s	32458.921us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	351.850s	8169.868us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	4389.260s	32458.921us	1	1	100.00
	chip_csr_rw	174.310s	4371.771us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	6.520s	218.992us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	302.050s	5190.290us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	302.050s	5190.290us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	302.050s	5190.290us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	350.380s	4885.889us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	350.380s	4885.889us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	326.830s	4265.673us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	381.190s	5322.898us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	339.690s	4622.813us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	374.740s	4746.378us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	419.240s	5407.648us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	691.530s	9434.636us	1	1	100.00

211/277 passed

76.17 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	184.580s	4764.192us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	184.580s	4764.192us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	253.180s	4080.811us	1	1	100.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	177.520s	3644.737us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	199.430s	4113.076us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	564.800s	9904.539us	1	1	100.00
	chip_tap_straps_testunlock0	172.220s	4938.696us	1	1	100.00
	chip_tap_straps_rma	179.620s	3843.132us	1	1	100.00
	chip_tap_straps_prod	697.420s	12022.735us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	494.390s	8106.930us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	494.390s	8106.930us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	714.620s	7846.595us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	1191.660s	13517.463us	0	1	0.00
chip_sw_ast_sys_clk_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	362.920s	4503.208us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	538.130s	6110.792us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3964.450s	19786.687us	1	1	100.00
	chip_sw_aes_enc_jitter_en	147.700s	2720.957us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	752.720s	8870.696us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	205.010s	4153.387us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1723.640s	14752.123us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	201.850s	3379.186us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	389.560s	4915.984us	1	1	100.00
	chip_sw_clkmgr_jitter	217.900s	3821.824us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	233.830s	3949.924us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				2	2	100.00
	chip_sw_sensor_ctrl_alert	659.250s	11336.865us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	284.730s	5607.614us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	164.980s	3251.148us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	284.730s	5607.614us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	136.860s	3132.631us	1	1	100.00
	chip_sw_aes_smoketest	184.790s	2824.263us	1	1	100.00
	chip_sw_aon_timer_smoketest	199.260s	3982.595us	1	1	100.00
	chip_sw_clkmgr_smoketest	192.130s	2931.054us	1	1	100.00
	chip_sw_csrng_smoketest	171.660s	3577.792us	1	1	100.00
	chip_sw_entropy_src_smoketest	843.000s	7651.238us	1	1	100.00
	chip_sw_gpio_smoketest	259.500s	4222.740us	1	1	100.00
	chip_sw_hmac_smoketest	238.740s	4003.242us	1	1	100.00
	chip_sw_kmac_smoketest	203.870s	3985.763us	1	1	100.00
	chip_sw_otbn_smoketest	1336.310s	9661.907us	1	1	100.00
	chip_sw_pwrmgr_smoketest	337.390s	7886.432us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	362.230s	7013.316us	1	1	100.00
	chip_sw_rv_plic_smoketest	175.870s	3539.543us	1	1	100.00
	chip_sw_rv_timer_smoketest	200.790s	4102.798us	1	1	100.00
	chip_sw_rstmgr_smoketest	178.790s	4198.550us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	180.100s	3231.308us	1	1	100.00
	chip_sw_uart_smoketest	206.000s	3788.061us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	189.370s	3716.852us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	398.670s	6706.282us	0	1	0.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	7846.690s	60425.496us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3119.780s	16205.931us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	155.978s	0.000us	0	1	0.00
chip_sw_power_idle_load				0	1	0.00
	chip_sw_power_idle_load	1124.510s	15419.965us	0	1	0.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	909.370s	15325.363us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	6918.300s	56264.466us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	7823.780s	57153.104us	1	1	100.00
tl_d_oob_addr_access				0	1	0.00
	chip_tl_errors	82.890s	3134.513us	0	1	0.00
tl_d_illegal_access				0	1	0.00
	chip_tl_errors	82.890s	3134.513us	0	1	0.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	4389.260s	32458.921us	1	1	100.00
	chip_same_csr_outstanding	1069.400s	15540.566us	1	1	100.00
	chip_csr_hw_reset	151.190s	4547.310us	1	1	100.00
	chip_csr_rw	174.310s	4371.771us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	4389.260s	32458.921us	1	1	100.00
	chip_same_csr_outstanding	1069.400s	15540.566us	1	1	100.00
	chip_csr_hw_reset	151.190s	4547.310us	1	1	100.00
	chip_csr_rw	174.310s	4371.771us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	35.030s	1432.547us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	4.440s	49.579us	1	1	100.00
	xbar_smoke_large_delays	46.480s	7993.825us	1	1	100.00
	xbar_smoke_slow_rsp	25.170s	2903.294us	1	1	100.00
	xbar_random_zero_delays	21.810s	346.011us	1	1	100.00
	xbar_random_large_delays	22.310s	3370.172us	1	1	100.00
	xbar_random_slow_rsp	99.910s	11063.999us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	13.400s	161.934us	1	1	100.00
	xbar_error_and_unmapped_addr	13.780s	192.584us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	16.200s	568.249us	1	1	100.00
	xbar_error_and_unmapped_addr	13.780s	192.584us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	27.130s	1077.199us	1	1	100.00
	xbar_access_same_device_slow_rsp	621.740s	75081.650us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	48.720s	2445.887us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	94.450s	3594.679us	1	1	100.00
	xbar_stress_all_with_error	335.440s	13653.540us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	8.450s	54.052us	1	1	100.00
	xbar_stress_all_with_reset_error	14.860s	89.531us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3119.780s	16205.931us	1	1	100.00
rom_e2e_shutdown_output				0	1	0.00
	rom_e2e_shutdown_output	395.780s	8308.133us	0	1	0.00
rom_e2e_shutdown_exception_c				0	1	0.00
	rom_e2e_shutdown_exception_c	362.700s	5133.434us	0	1	0.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	107.300s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	19.791s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	25.763s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	19.269s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	29.906s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	51.463s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	38.318s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	22.250s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	30.681s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	33.674s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	121.863s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	36.356s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	115.794s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	16.940s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	25.428s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	22.170s	10.120us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	18.140s	10.160us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	18.190s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	18.410s	10.340us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	17.850s	10.320us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	20.060s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	18.290s	10.200us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	19.080s	10.140us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	18.670s	10.220us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	18.650s	10.160us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	20.740s	10.400us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	18.150s	10.120us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	18.550s	10.240us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	18.240s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	18.160s	10.340us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	54.394s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	69.943s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	62.621s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	134.791s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	46.204s	0.000us	0	1	0.00
rom_e2e_keymgr_init				3	3	100.00
	rom_e2e_keymgr_init_rom_ext_meas	6051.310s	29110.235us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_no_meas	6072.350s	29349.108us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	6212.500s	28874.061us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3304.650s	17216.725us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3413.740s	34781.222us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3413.740s	34781.222us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	201.230s	3238.515us	1	1	100.00
	chip_sw_aes_enc_jitter_en	147.700s	2720.957us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	206.780s	3414.801us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	150.470s	3518.500us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	1121.170s	8965.248us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	168.330s	3214.653us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	396.590s	7421.171us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	566.740s	7757.768us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	472.370s	5740.555us	1	1	100.00
	chip_plic_all_irqs_10	269.720s	3846.265us	1	1	100.00
	chip_plic_all_irqs_20	353.400s	4642.071us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	214.710s	4025.641us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1091.820s	17740.238us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	325.220s	5397.425us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	205.110s	4455.357us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	14400.151s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	932.200s	8701.131us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1069.400s	9136.057us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	863.480s	8010.127us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	9770.240s	255692.098us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	227.500s	3980.726us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	337.390s	7886.432us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	227.500s	3980.726us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	368.670s	7818.428us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	368.670s	7818.428us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	390.640s	8699.509us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	359.180s	6671.140us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	608.950s	5891.063us	1	1	100.00
	chip_sw_aes_idle	150.470s	3518.500us	1	1	100.00
	chip_sw_hmac_enc_idle	204.920s	4109.375us	1	1	100.00
	chip_sw_kmac_idle	145.020s	2987.241us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	311.370s	5247.495us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	351.070s	4940.287us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	273.190s	4753.021us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	257.050s	5580.519us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	1019.670s	11750.795us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	428.100s	4638.221us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	426.750s	5514.782us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	485.430s	4960.836us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	454.310s	5980.281us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	394.580s	4447.702us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	389.080s	5428.841us	1	1	100.00
	chip_sw_ast_clk_outputs	714.620s	7846.595us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	429.600s	8154.006us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	485.430s	4960.836us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	454.310s	5980.281us	1	1	100.00
chip_sw_clkmgr_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	362.920s	4503.208us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	538.130s	6110.792us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3964.450s	19786.687us	1	1	100.00
	chip_sw_aes_enc_jitter_en	147.700s	2720.957us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	752.720s	8870.696us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	205.010s	4153.387us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1723.640s	14752.123us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	201.850s	3379.186us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	389.560s	4915.984us	1	1	100.00
	chip_sw_clkmgr_jitter	217.900s	3821.824us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	145.520s	2987.487us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	365.540s	5125.749us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	627.750s	7237.395us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	3963.740s	25018.342us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	175.800s	3839.778us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	194.790s	4197.177us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	950.480s	10796.320us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	220.090s	4158.244us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	386.410s	6049.992us	1	1	100.00
	chip_sw_flash_init_reduced_freq	1571.590s	30298.701us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	11173.880s	126381.804us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	714.620s	7846.595us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	371.580s	5125.977us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	317.510s	4854.253us	1	1	100.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	566.740s	7757.768us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	932.200s	8701.131us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	1790.190s	25188.983us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				1	1	100.00
	chip_sw_csrng_fuse_en_sw_app_read_test	336.420s	6243.993us	1	1	100.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	532.960s	7727.072us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	224.870s	3427.585us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	1485.080s	10115.955us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	192.170s	3821.084us	1	1	100.00
	chip_sw_edn_entropy_reqs	627.760s	6474.662us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	192.170s	3821.084us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	1790.190s	25188.983us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	205.170s	2899.822us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	1243.310s	20354.323us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	625.170s	6016.849us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	538.130s	6110.792us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	398.050s	4927.218us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	362.920s	4503.208us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	3147.130s	43952.893us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	1243.310s	20354.323us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	269.890s	3907.351us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	995.580s	8698.864us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	174.440s	3016.035us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	3147.130s	43952.893us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	174.440s	3016.035us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	174.440s	3016.035us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	174.440s	3016.035us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	174.440s	3016.035us	0	1	0.00
chip_sw_flash_lc_escalate_en				1	1	100.00
	chip_sw_all_escalation_resets	566.740s	7757.768us	1	1	100.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	413.010s	11144.319us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	623.890s	6105.634us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	445.280s	7764.854us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	445.280s	7764.854us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	192.040s	3684.589us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	205.010s	4153.387us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	204.920s	4109.375us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	1549.410s	11283.935us	1	1	100.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	1742.390s	12026.776us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	447.690s	5331.557us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	381.110s	5219.445us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	405.080s	4884.840us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	367.440s	5182.290us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	995.580s	8698.864us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1723.640s	14752.123us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	1211.300s	11308.979us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	1121.170s	8965.248us	1	1	100.00
chip_sw_keymgr_sideload_otbn				0	1	0.00
	chip_sw_keymgr_sideload_otbn	4457.190s	20026.760us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	178.710s	2658.076us	1	1	100.00
	chip_sw_kmac_mode_kmac	253.550s	3978.722us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	201.850s	3379.186us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	995.580s	8698.864us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	863.000s	17492.615us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	165.490s	3826.713us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	1684.040s	11815.834us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	145.020s	2987.241us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	396.590s	7421.171us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	564.800s	9904.539us	1	1	100.00
	chip_tap_straps_rma	179.620s	3843.132us	1	1	100.00
	chip_tap_straps_prod	697.420s	12022.735us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	203.460s	3765.419us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	863.000s	17492.615us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	863.000s	17492.615us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	863.000s	17492.615us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	828.370s	7376.523us	1	1	100.00
chip_sw_lc_ctrl_broadcast				19	22	86.36
	chip_sw_flash_ctrl_lc_rw_en	174.440s	3016.035us	0	1	0.00
	chip_sw_flash_rma_unlocked	3147.130s	43952.893us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	201.040s	4248.256us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	578.510s	6778.746us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	550.060s	7710.395us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	545.960s	8837.670us	0	1	0.00
	chip_sw_lc_ctrl_transition	863.000s	17492.615us	1	1	100.00
	chip_sw_keymgr_key_derivation	995.580s	8698.864us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	378.910s	11405.507us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	559.140s	10887.515us	1	1	100.00
	chip_prim_tl_access	413.010s	11144.319us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	429.600s	8154.006us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	428.100s	4638.221us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	426.750s	5514.782us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	485.430s	4960.836us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	454.310s	5980.281us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	394.580s	4447.702us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	389.080s	5428.841us	1	1	100.00
	chip_tap_straps_dev	564.800s	9904.539us	1	1	100.00
	chip_tap_straps_rma	179.620s	3843.132us	1	1	100.00
	chip_tap_straps_prod	697.420s	12022.735us	1	1	100.00
	chip_rv_dm_lc_disabled	62.660s	3027.365us	0	1	0.00
chip_lc_scrap				4	4	100.00
	chip_sw_lc_ctrl_rma_to_scrap	224.550s	3994.147us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	110.960s	4211.729us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	134.270s	4616.150us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	107.760s	3360.555us	1	1	100.00
chip_lc_test_locked				1	2	50.00
	chip_sw_lc_walkthrough_testunlocks	1907.430s	44732.330us	1	1	100.00
	chip_rv_dm_lc_disabled	62.660s	3027.365us	0	1	0.00
chip_sw_lc_walkthrough				2	5	40.00
	chip_sw_lc_walkthrough_dev	756.570s	15175.482us	0	1	0.00
	chip_sw_lc_walkthrough_prod	593.640s	12048.264us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	760.210s	14021.704us	1	1	100.00
	chip_sw_lc_walkthrough_rma	369.530s	7181.164us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	1907.430s	44732.330us	1	1	100.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	75.180s	2263.482us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	77.160s	3638.784us	1	1	100.00
	rom_volatile_raw_unlock	30.845s	0.000us	0	1	0.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	3896.330s	17481.892us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3964.450s	19786.687us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	608.950s	5891.063us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	608.950s	5891.063us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	608.950s	5891.063us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	309.190s	4329.741us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	863.000s	17492.615us	1	1	100.00
chip_sw_otp_ctrl_keys				5	5	100.00
	chip_sw_flash_init	1243.310s	20354.323us	1	1	100.00
	chip_sw_otbn_mem_scramble	309.190s	4329.741us	1	1	100.00
	chip_sw_keymgr_key_derivation	995.580s	8698.864us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	405.420s	6086.413us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	209.140s	3183.309us	1	1	100.00
chip_sw_otp_ctrl_entropy				5	5	100.00
	chip_sw_flash_init	1243.310s	20354.323us	1	1	100.00
	chip_sw_otbn_mem_scramble	309.190s	4329.741us	1	1	100.00
	chip_sw_keymgr_key_derivation	995.580s	8698.864us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	405.420s	6086.413us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	209.140s	3183.309us	1	1	100.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	863.000s	17492.615us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	394.290s	5445.848us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	203.460s	3765.419us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				5	6	83.33
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	201.040s	4248.256us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	578.510s	6778.746us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	550.060s	7710.395us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	545.960s	8837.670us	0	1	0.00
	chip_sw_lc_ctrl_transition	863.000s	17492.615us	1	1	100.00
	chip_prim_tl_access	413.010s	11144.319us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	413.010s	11144.319us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	737.250s	7762.341us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	74.850s	2323.198us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	931.740s	30757.424us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	293.130s	7966.613us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_deep_sleep_por_reset	405.800s	8418.420us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	347.200s	6220.261us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	1209.330s	25498.651us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				0	2	0.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	223.020s	6693.994us	0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	368.670s	7818.428us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	925.060s	11893.662us	1	1	100.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	373.570s	5198.964us	1	1	100.00
chip_sw_pwrmgr_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	74.850s	2323.198us	0	1	0.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	277.800s	5677.704us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	197.630s	5902.812us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	426.760s	9513.815us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	219.500s	3727.194us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	236.990s	7424.707us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	818.270s	11297.475us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	814.560s	13989.332us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1619.860s	35303.019us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	197.900s	3384.234us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	566.740s	7757.768us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	378.910s	11405.507us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	378.910s	11405.507us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	814.560s	13989.332us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	236.990s	7424.707us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	373.570s	5198.964us	1	1	100.00
	chip_sw_pwrmgr_smoketest	337.390s	7886.432us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	385.350s	6704.155us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	468.410s	8288.458us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	344.010s	5229.262us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1091.820s	17740.238us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	133.590s	3334.885us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	566.740s	7757.768us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1069.400s	9136.057us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	496.610s	5622.170us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	517.670s	5435.631us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	163.260s	3579.850us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	209.140s	3183.309us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	468.410s	8288.458us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	468.410s	8288.458us	1	1	100.00
chip_sw_rv_core_ibex_mcounteren_writable				1	1	100.00
	chip_sw_rv_core_ibex_mcounteren_writable	174.140s	3831.686us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	1115.830s	16607.831us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	1072.900s	16679.822us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	385.350s	6704.155us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	178.480s	3418.809us	0	1	0.00
chip_rv_dm_access_after_wakeup				0	1	0.00
	chip_sw_rv_dm_access_after_wakeup	1349.940s	14096.870us	0	1	0.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	179.620s	3843.132us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	62.660s	3027.365us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	472.370s	5740.555us	1	1	100.00
	chip_plic_all_irqs_10	269.720s	3846.265us	1	1	100.00
	chip_plic_all_irqs_20	353.400s	4642.071us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	173.320s	2731.939us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	188.030s	4102.340us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3119.780s	16205.931us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	254.560s	4416.126us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	221.240s	3985.446us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	251.740s	3722.735us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	209.460s	3867.648us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	405.420s	6086.413us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	389.560s	4915.984us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	418.270s	9925.724us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	426.570s	8249.187us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	559.140s	10887.515us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	566.740s	7757.768us	1	1	100.00
	chip_sw_data_integrity_escalation	494.390s	8106.930us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	818.270s	11297.475us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1016.080s	24269.405us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	221.920s	3992.442us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	291.690s	4401.474us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	363.200s	5385.766us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1016.080s	24269.405us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1016.080s	24269.405us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2205.830s	20975.071us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2205.830s	20975.071us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	307.350s	7646.239us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3413.740s	34781.222us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	170.930s	3425.158us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	233.610s	4041.033us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	290.120s	4184.388us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	391.520s	4675.445us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	947.900s	8313.989us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	5271.050s	32201.432us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	1854.910s	12572.292us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	177.660s	3429.083us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	202.330s	3435.180us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				1	1	100.00
	chip_sw_rv_core_ibex_lockstep_glitch	168.880s	3375.968us	1	1	100.00

16/26 passed

61.54 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	9760.410s	68945.365us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1034.030s	6983.906us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	482.930s	7308.526us	0	1	0.00
	rom_e2e_jtag_debug_dev	479.710s	8158.721us	0	1	0.00
	rom_e2e_jtag_debug_rma	205.740s	5065.634us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	99.100s	2769.811us	0	1	0.00
	rom_e2e_jtag_inject_dev	88.320s	2528.344us	0	1	0.00
	rom_e2e_jtag_inject_rma	92.120s	3998.215us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	40.168s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	283.300s	4812.313us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	297.130s	3471.659us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	938.590s	6259.714us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	1220.850s	8799.331us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	286.610s	3309.618us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	710.960s	6625.629us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				1	1	100.00
	chip_sw_otp_ctrl_vendor_test_csr_access	220.590s	3908.249us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	211.400s	3923.864us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				0	1	0.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	429.970s	8505.102us	0	1	0.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	337.120s	5264.276us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	814.560s	13989.332us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	482.930s	7308.526us	0	1	0.00
	rom_e2e_jtag_debug_dev	479.710s	8158.721us	0	1	0.00
	rom_e2e_jtag_debug_rma	205.740s	5065.634us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	332.950s	5334.201us	1	1	100.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	566.740s	7757.768us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5133.780s	38543.955us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5133.780s	38543.955us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				1	1	100.00
	chip_sw_spi_device_pinmux_sleep_retention	212.170s	3726.114us	1	1	100.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	350.380s	4885.889us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3176.080s	19133.245us	1	1	100.00

unmapped

7/11 passed

63.64 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				7	11	63.64
	chip_sival_flash_info_access	246.870s	4541.598us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	23.030s	10.260us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	6.180s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	165.020s	3073.650us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	177.730s	3862.420us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	250.470s	4845.737us	1	1	100.00
	chip_sw_pwrmgr_sleep_wake_5_bug	8.813s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	232.010s	4171.899us	1	1	100.00
	ate_bootstrap_flash_erase	549.940s	10010.140us	0	1	0.00
	ate_bootstrap_one_frame	6326.540s	44254.227us	1	1	100.00
	ate_bootstrap_disjoint	9574.890s	78963.446us	1	1	100.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				24 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	61862897924058882211778237145553130004047648175317479351975465700015679534593	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	54804124036730478596752089103570793275155460869520423425190743614133934072841	None	Another command (pid=464987) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=422439) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=558606) is running. Waiting for it to complete on the server (server_pid=273346)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	90796687507682277982551313028075573090364299253144587802131670401719929059308	None	Another command (pid=463801) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=577230) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=580804) is running. Waiting for it to complete on the server (server_pid=273346)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	106600455329509914476278352919704851557543646639784282142450503030969030059615	None	Another command (pid=577576) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=574051) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=613998) is running. Waiting for it to complete on the server (server_pid=273346)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	37425772309063006550007681018033342996532600124020272318374672663638549186280	None	Another command (pid=580804) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=588129) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=588578) is running. Waiting for it to complete on the server (server_pid=273346)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	81095877510221293434884532401445825174754813245392163415161206332772060050928	None	Another command (pid=628227) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=638970) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=642697) is running. Waiting for it to complete on the server (server_pid=273346)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	752837979463115746875000163116343240145776976686527085470994552477268470139	None	Another command (pid=378021) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=396830) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=390760) is running. Waiting for it to complete on the server (server_pid=273346)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	27736728649100075947593982303241270711037229264936906643566610205096405665173	None	Another command (pid=617298) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=586435) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=639922) is running. Waiting for it to complete on the server (server_pid=273346)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	115644011417314563878813587705805912268945655882086243075154141228790379437253	None	Another command (pid=548940) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=580804) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=588578) is running. Waiting for it to complete on the server (server_pid=273346)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	85495615228899912377337126712284888767672797681585391158009581138349010387087	None	Another command (pid=613998) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=611110) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=626432) is running. Waiting for it to complete on the server (server_pid=273346)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	27542935155293594343026946154686432114017805254139579562764604105775679570896	None	Another command (pid=585858) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=630709) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=576678) is running. Waiting for it to complete on the server (server_pid=273346)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	88183918472360538674568768445694535271864956570843756756938297470310822296277	None	---- STDERR ---- Another command (pid=568091) is running. Waiting for it to complete on the server (server_pid=273346)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	50832422975408370162460505990656202270236341106144258373886446785626429745341	None	---- STDERR ---- Another command (pid=510254) is running. Waiting for it to complete on the server (server_pid=273346)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	108081560129097715817079889413180473751477721273545384529406866489188852814749	None	Another command (pid=786789) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=777017) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=779091) is running. Waiting for it to complete on the server (server_pid=273346)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	89432377954213773924235232287576933517036188093280203801547349266694110152693	None	---- STDERR ---- Another command (pid=559799) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=424535) is running. Waiting for it to complete on the server (server_pid=273346)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	74379010550669552931074219704885808836871834891959547554757763965684776682818	None	---- STDERR ---- Another command (pid=580804) is running. Waiting for it to complete on the server (server_pid=273346)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	70657338432723692514556437359204426072691037501226391295533241808641823005473	None	Another command (pid=396830) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=390760) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=436766) is running. Waiting for it to complete on the server (server_pid=273346)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	83261857105849132769026769517537321418418076747085725208473900638709317481020	None	Another command (pid=402679) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=568091) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=573650) is running. Waiting for it to complete on the server (server_pid=273346)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	43129032545988046742481091263017583877139054081177424539752150708572875783965	None	---- STDERR ---- Another command (pid=465690) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=464987) is running. Waiting for it to complete on the server (server_pid=273346)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	35454430947207056724752031583155579668606322405212829583281571297153864987634	None	Another command (pid=441280) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=693365) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=699026) is running. Waiting for it to complete on the server (server_pid=273346)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	75308250457766011087232252246372314387510389418627125196647383232737395378817	None	Another command (pid=549109) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=424535) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=481600) is running. Waiting for it to complete on the server (server_pid=273346)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	52489591672807096028079848063362315836138189818285708442642913697303269326809	None	Another command (pid=390760) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=436766) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=449946) is running. Waiting for it to complete on the server (server_pid=273346)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	111647878532757224865915926169783815062071632695069889563903133191872359075995	None	Another command (pid=661166) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=679772) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=625184) is running. Waiting for it to complete on the server (server_pid=273346)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	33986310435229567500355224398089662427994782996035976854827495891356982435893	None	Another command (pid=390760) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=436766) is running. Waiting for it to complete on the server (server_pid=273346)... Another command (pid=403564) is running. Waiting for it to complete on the server (server_pid=273346)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access				7 test runs
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	114608391120225358506198862712226066627026921434712076178080643323653506865327	333	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_test_unlocked0	89035081461291604119641631031309299884287740461482593260620599753562279011029	358	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_dev	47673623050123050517271752727020899491890105231395284188418545241355898186336	358	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_rma	47686354318448560576259463954039132768907850563969832025663344147879363186599	325	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	79737660724010445093007594695283989815502433301680504032964619060581708701879	313	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	37791276866990839457674178147722628568922232880762805891205127723690273242712	311	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	14860896378381534097104683240494992631778731985796290305290428166241805899364	309	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				6 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_prod	75389249347613574905208085662313765228586326205838208397364337501633763730495	374	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	47405889011593374254332702405974166016320584836699761788725407514074622265156	374	UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_rma	74430985842091116735875252385213152861997857919799725594057263736911672077623	370	UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	79221889984951061178225218501779805312924146511156036119958813091744840438115	332	UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	47927491207793140151129359556723123650731564861020823462864296070716108097791	334	UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	53357650574819335263558054524114275963469692389436982545771048578808745221842	334	UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'				5 test runs
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	112930942254083107048726491835503629701520381070864152709028450996015144113433	321	UVM_ERROR @ 7424.706500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7424.706500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	29794940456838245944660864676150400793192693099236691303837650641794927316991	320	UVM_ERROR @ 6693.994000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 6693.994000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_por_reset	106280632138625375133395914624068926182967779091870966247648667871693499457753	331	UVM_ERROR @ 8418.420000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 8418.420000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	61972228503739148812723712092174052513325355165026734280628475740699148992541	322	UVM_ERROR @ 5902.812500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 5902.812500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_aon_timer_wdog_bite_reset	105867631462405842131893858789882497028902200579831265347616387434231203664044	325	UVM_ERROR @ 7818.428000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7818.428000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	98300387948666629771115685293679521583408694583955005858096374197945209129976	375	UVM_INFO @ 15175.481650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	28260983378018752938053786565633512021869231845059625399224827859195609923587	370	UVM_INFO @ 12048.264468 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	14772030264991981198318123787327978605518434520418675762499671019575841094629	342	UVM_INFO @ 7181.164382 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				3 test runs
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	110268759307411265581360470138365714140294422859416921481486561745822748756567	334	UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	29146752213326841196881628487351307043345764270450586617935865888577029947833	334	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	56843848105315919575484042011103233876879576200056467761059152444768549917753	334	UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				2 test runs
	chip_sw_hmac_multistream	35932587860667043760819275247227468633218870919414973590543175269475232347756	373	UVM_INFO @ 12026.775702 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_keymgr_sideload_otbn	62188981034805174267278491302767269175711432230638429249348935237666842900072	342	UVM_INFO @ 20026.760421 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	105416076243390653209864942269807217303144929742388154874965262797123379940952	369	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	82141180398153363796499273674964039245998105452373156119144933942981318366180	326	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_dev	90775934251017861219900269181531647787578851033612734178784707606690644994253	374	UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	84575774667639584474257474510297162983516466982649468837329435244419954308347	334	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	2417549098645107592283131496406068611334551611578520303592017656067792905742	307	UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty				1 test run
	chip_sw_spi_device_pass_through_collision	85888467845210721199320042325603057750020567781748236166232773370835048130384	328	UVM_INFO @ 3985.446468 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_flash_ctrl_lc_rw_en	113338385779763283044362635267001731644739916712050519882427769684091449276403	310	UVM_INFO @ 3016.035200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	19162388461817973783075882403695837537080905462955358167653154304124491373218	343	UVM_INFO @ 8837.670000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				1 test run
	chip_sw_otp_ctrl_escalation	91633708520101031899625025881307179490634289011504266097412458929298833317031	317	UVM_ERROR @ 3923.864400 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3923.864400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode				1 test run
	chip_sw_otp_ctrl_rot_auth_config	98940922908617851104969958758511386179919196499881957183858319950556187546025	283	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'				1 test run
	chip_sw_pwrmgr_full_aon_reset	60286014241735514812018276154361513594773799350116474263191546495824839340761	309	UVM_ERROR @ 2323.197858 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A UVM_INFO @ 2323.197858 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				1 test run
	chip_sw_pwrmgr_sleep_power_glitch_reset	92544676314596739348738946774365547575880687880397599684462934680745764191944	314	UVM_ERROR @ 3727.193890 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 3727.193890 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	90599944261138081007683983431790676950219525031817049078239086142095036954441	338	UVM_INFO @ 34781.221622 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:361)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	51047837511430158473837966573975482412670645172638326173903493324568534652889	313	UVM_INFO @ 3214.652901 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	113251942061145059673981736541694384688301903916603975539720510187140626851593	314	UVM_INFO @ 4455.356740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_pings	94821602812951001822278740779454586929174443849913253328705035989586678756486	None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted , but saw ).				1 test run
	chip_tl_errors	102199349890268022440437885576844140058565827404778335732366682994401440342131	218	TL item was: req: (cip_tl_seq_item@31282) { a_addr: 'h1063c a_data: 'h63628e8e a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1a a_opcode: 'h4 a_user: 'h1bae9 d_param: 'h0 d_source: 'h1a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 3134.512728 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	19141084346573702654804708753963837051795458143043606286659199125340987808049	349	UVM_INFO @ 4812.312924 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: *				1 test run
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	82396793210606875000459730753490719565876074720255122736054348931336444223455	317	UVM_INFO @ 8505.102496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep.				1 test run
	chip_sw_rv_dm_access_after_wakeup	2332955783314041924670041638207674432169359348714895678417790279328912862223	330	UVM_INFO @ 14096.870206 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				1 test run
	chip_rv_dm_lc_disabled	101479461632955776978405344139522350985461626874721541914898475859620367032556	222	UVM_INFO @ 3027.364956 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*)				1 test run
	chip_sw_power_idle_load	19705426516916002568486168201096728794262620918907460540239130717228898171033	319	UVM_INFO @ 15419.964572 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*)				1 test run
	chip_sw_power_sleep_load	10946606002395831977841130810220476287375882668781305494970322628461766220815	335	UVM_INFO @ 15325.363400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	68743312893226609935414832985523478186161978412028023138534737440369241596633	333	UVM_INFO @ 13517.463266 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	115149269688378429871616194718482212512627198381345291237413192510029895991477	278	UVM_INFO @ 10010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:--*				1 test run
	rom_e2e_shutdown_exception_c	8843680994663865333964420690552492336641067062190294364032231289629570395222	325	" == "OpenTitan:4001-0002-01 " UVM_INFO @ 5133.434337 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:--*				1 test run
	rom_e2e_shutdown_output	103080099459802920094999328849881542922794392360705858792575828435528136201530	318	" == "OpenTitan:4001-0002-01 " UVM_INFO @ 8308.133129 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	80168407155614213493872709005122261415886354519862923325371930134221248497439	331	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	7294957183408228755705997365071392373255894645771211455540583103793732920854	334	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'				1 test run
	rom_keymgr_functest	21357426306631265781343523787539168908595372928358216774889715084124010967866	328	UVM_ERROR @ 6706.282346 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 6706.282346 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---