Simulation Results: clkmgr

 
29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.85 %
  • code
  • 97.62 %
  • assert
  • 93.36 %
  • func
  • 84.56 %
  • line
  • 98.85 %
  • branch
  • 98.69 %
  • cond
  • 91.37 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.810s 37.576us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.920s 106.510us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.760s 28.175us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 5.680s 1538.692us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.360s 99.704us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.320s 155.277us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.760s 28.175us 1 1 100.00
clkmgr_csr_aliasing 1.360s 99.704us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.730s 15.743us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.770s 29.635us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.750s 26.939us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.710s 18.278us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.810s 37.576us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 6.780s 2124.105us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 3.670s 1296.400us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 6.780s 2124.105us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 4.840s 1580.755us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.880s 29.061us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.780s 131.203us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.780s 131.203us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.920s 106.510us 1 1 100.00
clkmgr_csr_rw 0.760s 28.175us 1 1 100.00
clkmgr_csr_aliasing 1.360s 99.704us 1 1 100.00
clkmgr_same_csr_outstanding 0.920s 32.869us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.920s 106.510us 1 1 100.00
clkmgr_csr_rw 0.760s 28.175us 1 1 100.00
clkmgr_csr_aliasing 1.360s 99.704us 1 1 100.00
clkmgr_same_csr_outstanding 0.920s 32.869us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 42.360s 10025.768us 0 1 0.00
clkmgr_tl_intg_err 2.100s 146.320us 1 1 100.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 547.340s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 547.340s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 547.340s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 547.340s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.510s 80.241us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 2.100s 146.320us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 6.780s 2124.105us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 3.670s 1296.400us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 547.340s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.500s 129.719us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.890s 29.766us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.780s 49.162us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.930s 20.568us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.840s 26.956us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.760s 28.175us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 42.360s 10025.768us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.760s 28.175us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.760s 28.175us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 42.360s 10025.768us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.040s 219.348us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 20.290s 2243.508us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 93421096458847371273632967931579351510084398841544453265367911859640799810898 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_sec_cm 28328376671885852686113824365228860797895299656545926419112621907435883952196 99
UVM_INFO @ 10025767806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---