Simulation Results: csrng

 
29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 85.58 %
  • code
  • 92.30 %
  • assert
  • 94.32 %
  • func
  • 70.11 %
  • block
  • 96.99 %
  • line
  • 97.73 %
  • branch
  • 92.51 %
  • toggle
  • 93.24 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 1.000s 24.426us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 3.000s 62.564us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 201.076us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 11.000s 338.879us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 161.132us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 25.140us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 201.076us 1 1 100.00
csrng_csr_aliasing 3.000s 161.132us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 248.258us 1 1 100.00
alerts 1 1 100.00
csrng_alert 11.000s 526.534us 1 1 100.00
err 1 1 100.00
csrng_err 1.000s 22.597us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 4.000s 175.211us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 4.000s 175.211us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 49.000s 1228.449us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 29.640us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 132.347us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 2.000s 91.147us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 2.000s 91.147us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 3.000s 62.564us 1 1 100.00
csrng_csr_rw 2.000s 201.076us 1 1 100.00
csrng_csr_aliasing 3.000s 161.132us 1 1 100.00
csrng_same_csr_outstanding 3.000s 48.406us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 3.000s 62.564us 1 1 100.00
csrng_csr_rw 2.000s 201.076us 1 1 100.00
csrng_csr_aliasing 3.000s 161.132us 1 1 100.00
csrng_same_csr_outstanding 3.000s 48.406us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 135.469us 1 1 100.00
csrng_tl_intg_err 2.000s 90.087us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 21.508us 1 1 100.00
csrng_csr_rw 2.000s 201.076us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 11.000s 526.534us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 49.000s 1228.449us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 248.258us 1 1 100.00
csrng_err 1.000s 22.597us 1 1 100.00
csrng_sec_cm 3.000s 135.469us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 248.258us 1 1 100.00
csrng_err 1.000s 22.597us 1 1 100.00
csrng_sec_cm 3.000s 135.469us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 248.258us 1 1 100.00
csrng_err 1.000s 22.597us 1 1 100.00
csrng_sec_cm 3.000s 135.469us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 248.258us 1 1 100.00
csrng_err 1.000s 22.597us 1 1 100.00
csrng_sec_cm 3.000s 135.469us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 248.258us 1 1 100.00
csrng_err 1.000s 22.597us 1 1 100.00
csrng_sec_cm 3.000s 135.469us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 11.000s 526.534us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 248.258us 1 1 100.00
csrng_err 1.000s 22.597us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 49.000s 1228.449us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 11.000s 526.534us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 2.000s 90.087us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 248.258us 1 1 100.00
csrng_err 1.000s 22.597us 1 1 100.00
csrng_sec_cm 3.000s 135.469us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 248.258us 1 1 100.00
csrng_err 1.000s 22.597us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 248.258us 1 1 100.00
csrng_err 1.000s 22.597us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 248.258us 1 1 100.00
csrng_err 1.000s 22.597us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 248.258us 1 1 100.00
csrng_err 1.000s 22.597us 1 1 100.00
csrng_sec_cm 3.000s 135.469us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 248.258us 1 1 100.00
csrng_err 1.000s 22.597us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3601.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 71969303986563685951046464551177891199428293308650937762819559272497512068574 100
UVM_INFO @ 175211206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 4126826017013352151685947296604531358119538402187281993839740581071191066485 None