Simulation Results: edn/edn0

 
29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.16 %
  • code
  • 72.40 %
  • assert
  • 93.28 %
  • func
  • 74.80 %
  • line
  • 94.62 %
  • branch
  • 82.57 %
  • cond
  • 77.37 %
  • toggle
  • 65.48 %
  • FSM
  • 41.94 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.830s 46.221us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.860s 20.227us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.800s 43.929us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.720s 97.600us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.130s 18.705us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.090s 41.327us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.800s 43.929us 1 1 100.00
edn_csr_aliasing 1.130s 18.705us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.190s 40.887us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.190s 40.887us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.190s 40.887us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.800s 27.042us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.990s 83.023us 1 1 100.00
errs 1 1 100.00
edn_err 0.910s 68.446us 1 1 100.00
disable 1 2 50.00
edn_disable 0.770s 16.936us 1 1 100.00
edn_disable_auto_req_mode 0.920s 54.826us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 3.600s 270.298us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.860s 18.681us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.940s 48.389us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.170s 319.213us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.170s 319.213us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.860s 20.227us 1 1 100.00
edn_csr_rw 0.800s 43.929us 1 1 100.00
edn_csr_aliasing 1.130s 18.705us 1 1 100.00
edn_same_csr_outstanding 1.450s 42.184us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.860s 20.227us 1 1 100.00
edn_csr_rw 0.800s 43.929us 1 1 100.00
edn_csr_aliasing 1.130s 18.705us 1 1 100.00
edn_same_csr_outstanding 1.450s 42.184us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.890s 782.190us 1 1 100.00
edn_tl_intg_err 2.560s 164.140us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.930s 30.619us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.990s 83.023us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.890s 782.190us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.890s 782.190us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.890s 782.190us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.890s 782.190us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.990s 83.023us 1 1 100.00
edn_sec_cm 3.890s 782.190us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.990s 83.023us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 2.560s 164.140us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 20.340s 4052.313us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 1 test run
edn_disable_auto_req_mode 39375212466374185052564645055366857554940517283907765318542643936945530632852 88
UVM_INFO @ 54826338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---