Simulation Results: edn/edn1

 
29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.86 %
  • code
  • 84.47 %
  • assert
  • 98.44 %
  • func
  • 80.67 %
  • line
  • 98.18 %
  • branch
  • 93.51 %
  • cond
  • 90.00 %
  • toggle
  • 95.19 %
  • FSM
  • 45.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.830s 18.858us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.830s 62.706us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.750s 24.021us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.490s 81.785us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.100s 53.012us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.210s 48.538us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.750s 24.021us 1 1 100.00
edn_csr_aliasing 1.100s 53.012us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.000s 169.253us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.000s 169.253us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.000s 169.253us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.910s 52.557us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.980s 71.065us 1 1 100.00
errs 1 1 100.00
edn_err 0.780s 110.242us 1 1 100.00
disable 2 2 100.00
edn_disable 0.750s 39.986us 1 1 100.00
edn_disable_auto_req_mode 0.920s 45.240us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.690s 734.055us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.770s 66.021us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.810s 22.144us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.010s 161.003us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.010s 161.003us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.830s 62.706us 1 1 100.00
edn_csr_rw 0.750s 24.021us 1 1 100.00
edn_csr_aliasing 1.100s 53.012us 1 1 100.00
edn_same_csr_outstanding 0.900s 73.153us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.830s 62.706us 1 1 100.00
edn_csr_rw 0.750s 24.021us 1 1 100.00
edn_csr_aliasing 1.100s 53.012us 1 1 100.00
edn_same_csr_outstanding 0.900s 73.153us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.190s 1154.681us 1 1 100.00
edn_tl_intg_err 1.300s 59.536us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.850s 129.091us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.980s 71.065us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.190s 1154.681us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.190s 1154.681us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.190s 1154.681us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.190s 1154.681us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.980s 71.065us 1 1 100.00
edn_sec_cm 3.190s 1154.681us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.980s 71.065us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.300s 59.536us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 55.080s 6658.330us 1 1 100.00