Simulation Results: flash_ctrl

 
29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.52 %
  • code
  • 93.02 %
  • assert
  • 94.64 %
  • func
  • 95.91 %
  • line
  • 95.93 %
  • branch
  • 96.75 %
  • cond
  • 93.00 %
  • toggle
  • 93.05 %
  • FSM
  • 86.39 %
Validation stages
V1
100.00%
V2
100.00%
V2S
95.83%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 58.410s 274.954us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 11.670s 53.641us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 15.420s 30.399us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.150s 27.461us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 25.670s 957.389us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 22.250s 1675.728us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 12.180s 213.639us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.150s 27.461us 1 1 100.00
flash_ctrl_csr_aliasing 22.250s 1675.728us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 5.970s 17.511us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.140s 60.720us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 11.640s 73.583us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 16.380s 28.246us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1206.200s 209364.638us 1 1 100.00
flash_ctrl_hw_rma_reset 477.790s 80146.261us 1 1 100.00
flash_ctrl_lcmgr_intg 6.110s 65.570us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1174.230s 1495051.229us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 203.760s 11265.778us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 6.170s 63.491us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2224.530s 54187.005us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 57.540s 5832.938us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 15.100s 45.492us 1 1 100.00
flash_ctrl_rw_evict_all_en 16.220s 33.856us 1 1 100.00
flash_ctrl_re_evict 16.360s 67.101us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 124.230s 4577.157us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 124.230s 4577.157us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 209.960s 19805.991us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 15.410s 1865.502us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 435.770s 397.804us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 352.880s 5833.407us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 374.560s 977.125us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 769.730s 1647.219us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.030s 24.619us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 124.980s 8532.210us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 11.540s 35.666us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 6.130s 69.847us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 13.810s 98.654us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 88.200s 19486.895us 1 1 100.00
flash_ctrl_otp_reset 61.120s 39.891us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1206.200s 209364.638us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 66.970s 986.209us 1 1 100.00
flash_ctrl_intr_wr 50.230s 3146.773us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 158.920s 12163.061us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 123.980s 51180.477us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 39.350s 2330.640us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 32.290s 682.648us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 10.290s 57.428us 1 1 100.00
flash_ctrl_ro_derr 100.930s 1845.876us 1 1 100.00
flash_ctrl_rw_derr 122.840s 4121.154us 1 1 100.00
flash_ctrl_derr_detect 99.140s 774.225us 1 1 100.00
flash_ctrl_integrity 335.700s 8125.983us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 11.030s 31.811us 1 1 100.00
flash_ctrl_ro_serr 125.820s 3963.487us 1 1 100.00
flash_ctrl_rw_serr 123.530s 3856.315us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 43.320s 853.692us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 45.180s 7344.854us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 121.580s 2954.914us 1 1 100.00
flash_ctrl_write_word_sweep 6.560s 43.055us 1 1 100.00
flash_ctrl_read_word_sweep 6.920s 29.319us 1 1 100.00
flash_ctrl_ro 87.870s 924.436us 1 1 100.00
flash_ctrl_rw 410.700s 10520.373us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 21.860s 387.854us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 529.840s 40359.789us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 41.310s 10035.543us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.160s 115.769us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.860s 18.828us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 8.210s 38.116us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 8.210s 38.116us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 15.420s 30.399us 1 1 100.00
flash_ctrl_csr_rw 8.150s 27.461us 1 1 100.00
flash_ctrl_csr_aliasing 22.250s 1675.728us 1 1 100.00
flash_ctrl_same_csr_outstanding 11.030s 181.188us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 15.420s 30.399us 1 1 100.00
flash_ctrl_csr_rw 8.150s 27.461us 1 1 100.00
flash_ctrl_csr_aliasing 22.250s 1675.728us 1 1 100.00
flash_ctrl_same_csr_outstanding 11.030s 181.188us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 22.400s 367.595us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 22.400s 367.595us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 22.400s 367.595us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 22.400s 367.595us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 23.930s 349.705us 1 1 100.00
tl_intg_err 1 2 50.00
flash_ctrl_sec_cm 113.500s 90.265us 0 1 0.00
flash_ctrl_tl_intg_err 211.190s 398.616us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 211.190s 398.616us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 211.190s 398.616us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 15.790s 91.121us 1 1 100.00
flash_ctrl_wr_intg 7.020s 51.564us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 58.410s 274.954us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 61.120s 39.891us 1 1 100.00
flash_ctrl_disable 11.540s 35.666us 1 1 100.00
flash_ctrl_sec_info_access 41.560s 2405.697us 1 1 100.00
flash_ctrl_connect 6.130s 69.847us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.130s 46.069us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.150s 27.461us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 22.400s 367.595us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.150s 27.461us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 22.400s 367.595us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.150s 27.461us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 22.400s 367.595us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 11.540s 35.666us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 15.790s 91.121us 1 1 100.00
flash_ctrl_access_after_disable 7.510s 32.658us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 16.250s 28.549us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 11.540s 35.666us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 15.410s 1865.502us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 410.700s 10520.373us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 123.530s 3856.315us 1 1 100.00
flash_ctrl_rw_derr 122.840s 4121.154us 1 1 100.00
flash_ctrl_integrity 335.700s 8125.983us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1206.200s 209364.638us 1 1 100.00
sec_cm_ctrl_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 113.500s 90.265us 0 1 0.00
sec_cm_phy_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 113.500s 90.265us 0 1 0.00
sec_cm_phy_prog_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 113.500s 90.265us 0 1 0.00
sec_cm_ctr_redun 0 1 0.00
flash_ctrl_sec_cm 113.500s 90.265us 0 1 0.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 8.010s 860.295us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.290s 23.878us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 7.320s 70.271us 1 1 100.00
sec_cm_fifo_ctr_redun 0 1 0.00
flash_ctrl_sec_cm 113.500s 90.265us 0 1 0.00
sec_cm_mem_tl_lc_gate_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 113.500s 90.265us 0 1 0.00
sec_cm_prog_tl_lc_gate_fsm_sparse 0 1 0.00
flash_ctrl_sec_cm 113.500s 90.265us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 23.310s 116.520us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 220.350s 1883.676us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (flash_ctrl_base_vseq.sv:188) [flash_ctrl_common_vseq] Check failed (!address_in_words(bank, part, addr)) Overwriting address * in part FlashPartData 1 test run
flash_ctrl_sec_cm 2261339388071551885723799164773958978439015340417967097012338100758991165401 587
UVM_INFO @ 90265.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---