Simulation Results: hmac

 
29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.86 %
  • code
  • 97.12 %
  • assert
  • 97.16 %
  • func
  • 42.30 %
  • line
  • 99.69 %
  • branch
  • 99.01 %
  • cond
  • 95.73 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 2.040s 200.389us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.680s 49.814us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.900s 33.220us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.740s 591.161us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.020s 553.159us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 0.910s 46.486us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.900s 33.220us 1 1 100.00
hmac_csr_aliasing 6.020s 553.159us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 25.280s 889.622us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 31.800s 11401.478us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 190.840s 8038.827us 1 1 100.00
hmac_test_sha384_vectors 20.020s 1255.902us 1 1 100.00
hmac_test_sha512_vectors 337.130s 56993.695us 1 1 100.00
hmac_test_hmac256_vectors 10.650s 1747.253us 1 1 100.00
hmac_test_hmac384_vectors 8.960s 1030.935us 1 1 100.00
hmac_test_hmac512_vectors 11.290s 930.813us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 22.970s 5230.819us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 297.150s 12480.589us 1 1 100.00
error 1 1 100.00
hmac_error 12.580s 6195.179us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 119.300s 13171.615us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 2.040s 200.389us 1 1 100.00
hmac_long_msg 25.280s 889.622us 1 1 100.00
hmac_back_pressure 31.800s 11401.478us 1 1 100.00
hmac_datapath_stress 297.150s 12480.589us 1 1 100.00
hmac_burst_wr 22.970s 5230.819us 1 1 100.00
hmac_stress_all 2066.900s 313570.024us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 2.040s 200.389us 1 1 100.00
hmac_long_msg 25.280s 889.622us 1 1 100.00
hmac_back_pressure 31.800s 11401.478us 1 1 100.00
hmac_datapath_stress 297.150s 12480.589us 1 1 100.00
hmac_wipe_secret 119.300s 13171.615us 1 1 100.00
hmac_test_sha256_vectors 190.840s 8038.827us 1 1 100.00
hmac_test_sha384_vectors 20.020s 1255.902us 1 1 100.00
hmac_test_sha512_vectors 337.130s 56993.695us 1 1 100.00
hmac_test_hmac256_vectors 10.650s 1747.253us 1 1 100.00
hmac_test_hmac384_vectors 8.960s 1030.935us 1 1 100.00
hmac_test_hmac512_vectors 11.290s 930.813us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 2.040s 200.389us 1 1 100.00
hmac_long_msg 25.280s 889.622us 1 1 100.00
hmac_back_pressure 31.800s 11401.478us 1 1 100.00
hmac_datapath_stress 297.150s 12480.589us 1 1 100.00
hmac_burst_wr 22.970s 5230.819us 1 1 100.00
hmac_error 12.580s 6195.179us 1 1 100.00
hmac_wipe_secret 119.300s 13171.615us 1 1 100.00
hmac_test_sha256_vectors 190.840s 8038.827us 1 1 100.00
hmac_test_sha384_vectors 20.020s 1255.902us 1 1 100.00
hmac_test_sha512_vectors 337.130s 56993.695us 1 1 100.00
hmac_test_hmac256_vectors 10.650s 1747.253us 1 1 100.00
hmac_test_hmac384_vectors 8.960s 1030.935us 1 1 100.00
hmac_test_hmac512_vectors 11.290s 930.813us 1 1 100.00
hmac_stress_all 2066.900s 313570.024us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 2066.900s 313570.024us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.600s 14.489us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.600s 14.344us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.870s 191.638us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.870s 191.638us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.680s 49.814us 1 1 100.00
hmac_csr_rw 0.900s 33.220us 1 1 100.00
hmac_csr_aliasing 6.020s 553.159us 1 1 100.00
hmac_same_csr_outstanding 1.150s 736.251us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.680s 49.814us 1 1 100.00
hmac_csr_rw 0.900s 33.220us 1 1 100.00
hmac_csr_aliasing 6.020s 553.159us 1 1 100.00
hmac_same_csr_outstanding 1.150s 736.251us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.220s 350.534us 1 1 100.00
hmac_tl_intg_err 2.400s 99.902us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.400s 99.902us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 2.040s 200.389us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.210s 496.231us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 22.810s 6716.856us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.890s 109.645us 1 1 100.00