Simulation Results: lc_ctrl/volatile_unlock_disabled

 
29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.72 %
  • code
  • 84.01 %
  • assert
  • 94.97 %
  • func
  • 93.19 %
  • line
  • 97.24 %
  • branch
  • 93.70 %
  • cond
  • 79.72 %
  • toggle
  • 86.77 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.930s 393.400us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.840s 249.909us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.920s 16.022us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.290s 125.727us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.010s 61.714us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.050s 26.241us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.920s 16.022us 1 1 100.00
lc_ctrl_csr_aliasing 1.010s 61.714us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.230s 104.985us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.460s 752.613us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.750s 39.204us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.620s 85.901us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.990s 1165.358us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.800s 328.255us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.990s 1165.358us 1 1 100.00
lc_ctrl_prog_failure 1.620s 85.901us 1 1 100.00
lc_ctrl_errors 4.800s 328.255us 1 1 100.00
lc_ctrl_security_escalation 5.640s 9873.440us 1 1 100.00
lc_ctrl_jtag_state_failure 39.530s 6818.424us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.840s 738.414us 1 1 100.00
lc_ctrl_jtag_errors 28.890s 14371.504us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.090s 734.264us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.670s 642.620us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.840s 738.414us 1 1 100.00
lc_ctrl_jtag_errors 28.890s 14371.504us 1 1 100.00
lc_ctrl_jtag_access 2.140s 907.475us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.400s 1246.591us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.300s 196.220us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.460s 150.162us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.640s 4629.141us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.230s 497.506us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.350s 24.594us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.040s 503.281us 1 1 100.00
lc_ctrl_jtag_alert_test 0.910s 44.254us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 11.860s 6273.960us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.780s 24.908us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 58.550s 12927.743us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.020s 33.287us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.730s 598.888us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.730s 598.888us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.840s 249.909us 1 1 100.00
lc_ctrl_csr_rw 0.920s 16.022us 1 1 100.00
lc_ctrl_csr_aliasing 1.010s 61.714us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.260s 48.147us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.840s 249.909us 1 1 100.00
lc_ctrl_csr_rw 0.920s 16.022us 1 1 100.00
lc_ctrl_csr_aliasing 1.010s 61.714us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.260s 48.147us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.590s 136.358us 1 1 100.00
lc_ctrl_tl_intg_err 1.950s 575.757us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.950s 575.757us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.460s 752.613us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.990s 1165.358us 1 1 100.00
lc_ctrl_sec_cm 5.590s 136.358us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.990s 1165.358us 1 1 100.00
lc_ctrl_sec_cm 5.590s 136.358us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.990s 1165.358us 1 1 100.00
lc_ctrl_sec_cm 5.590s 136.358us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.990s 1165.358us 1 1 100.00
lc_ctrl_sec_cm 5.590s 136.358us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.990s 1165.358us 1 1 100.00
lc_ctrl_sec_cm 5.590s 136.358us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.990s 1165.358us 1 1 100.00
lc_ctrl_sec_cm 5.590s 136.358us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.990s 1165.358us 1 1 100.00
lc_ctrl_sec_cm 5.590s 136.358us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.990s 1165.358us 1 1 100.00
lc_ctrl_sec_cm 5.590s 136.358us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.640s 9873.440us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.230s 104.985us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.670s 642.620us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 3.800s 407.379us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 3.800s 407.379us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.260s 540.099us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.560s 253.633us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.560s 253.633us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 51.010s 27686.134us 1 1 100.00