Simulation Results: lc_ctrl/volatile_unlock_enabled

 
29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.44 %
  • code
  • 83.83 %
  • assert
  • 94.83 %
  • func
  • 92.65 %
  • line
  • 97.17 %
  • branch
  • 93.66 %
  • cond
  • 79.41 %
  • toggle
  • 86.29 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.590s 172.667us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.780s 12.889us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.800s 15.680us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.150s 144.447us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.130s 146.793us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.160s 24.678us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.800s 15.680us 1 1 100.00
lc_ctrl_csr_aliasing 1.130s 146.793us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.330s 84.815us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.600s 327.342us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.730s 76.661us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.530s 100.590us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.620s 241.925us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.730s 672.156us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.620s 241.925us 1 1 100.00
lc_ctrl_prog_failure 1.530s 100.590us 1 1 100.00
lc_ctrl_errors 4.730s 672.156us 1 1 100.00
lc_ctrl_security_escalation 3.790s 1027.607us 1 1 100.00
lc_ctrl_jtag_state_failure 14.850s 4468.094us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.080s 2616.936us 1 1 100.00
lc_ctrl_jtag_errors 12.520s 4493.006us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.110s 1728.905us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.540s 924.395us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.080s 2616.936us 1 1 100.00
lc_ctrl_jtag_errors 12.520s 4493.006us 1 1 100.00
lc_ctrl_jtag_access 4.120s 1808.418us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.830s 2671.346us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.130s 216.164us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.380s 87.906us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.120s 5195.772us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.980s 702.164us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.010s 160.053us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.610s 498.093us 1 1 100.00
lc_ctrl_jtag_alert_test 0.780s 127.746us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.330s 289.693us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.700s 24.669us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 44.000s 4463.147us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.800s 28.321us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.310s 145.108us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.310s 145.108us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.780s 12.889us 1 1 100.00
lc_ctrl_csr_rw 0.800s 15.680us 1 1 100.00
lc_ctrl_csr_aliasing 1.130s 146.793us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.920s 17.080us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.780s 12.889us 1 1 100.00
lc_ctrl_csr_rw 0.800s 15.680us 1 1 100.00
lc_ctrl_csr_aliasing 1.130s 146.793us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.920s 17.080us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.210s 969.652us 1 1 100.00
lc_ctrl_tl_intg_err 1.110s 46.332us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.110s 46.332us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.600s 327.342us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.620s 241.925us 1 1 100.00
lc_ctrl_sec_cm 6.210s 969.652us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.620s 241.925us 1 1 100.00
lc_ctrl_sec_cm 6.210s 969.652us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.620s 241.925us 1 1 100.00
lc_ctrl_sec_cm 6.210s 969.652us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.620s 241.925us 1 1 100.00
lc_ctrl_sec_cm 6.210s 969.652us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.620s 241.925us 1 1 100.00
lc_ctrl_sec_cm 6.210s 969.652us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.620s 241.925us 1 1 100.00
lc_ctrl_sec_cm 6.210s 969.652us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.620s 241.925us 1 1 100.00
lc_ctrl_sec_cm 6.210s 969.652us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.620s 241.925us 1 1 100.00
lc_ctrl_sec_cm 6.210s 969.652us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.790s 1027.607us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.330s 84.815us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.540s 924.395us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 3.430s 959.665us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 3.430s 959.665us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.480s 2556.154us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.060s 1450.698us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.060s 1450.698us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 49.010s 2872.407us 1 1 100.00