Simulation Results: otbn

 
29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.66 %
  • code
  • 81.72 %
  • assert
  • 89.80 %
  • func
  • 97.46 %
  • block
  • 97.71 %
  • line
  • 97.91 %
  • branch
  • 81.81 %
  • toggle
  • 80.94 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
88.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 75.062us 1 1 100.00
single_binary 1 1 100.00
otbn_single 14.000s 65.452us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 20.000s 34.931us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 17.000s 45.280us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 23.000s 81.871us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 22.000s 22.068us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 22.000s 72.556us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 17.000s 45.280us 1 1 100.00
otbn_csr_aliasing 22.000s 22.068us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 50.000s 775.914us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 26.000s 337.731us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 41.000s 561.285us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 64.000s 218.056us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 47.000s 358.657us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 8.000s 64.543us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 18.000s 21.762us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 114.961us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 7.000s 37.903us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 25.000s 20.295us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 34.363us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 8.000s 163.490us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 8.000s 163.490us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 20.000s 34.931us 1 1 100.00
otbn_csr_rw 17.000s 45.280us 1 1 100.00
otbn_csr_aliasing 22.000s 22.068us 1 1 100.00
otbn_same_csr_outstanding 5.000s 122.521us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 20.000s 34.931us 1 1 100.00
otbn_csr_rw 17.000s 45.280us 1 1 100.00
otbn_csr_aliasing 22.000s 22.068us 1 1 100.00
otbn_same_csr_outstanding 5.000s 122.521us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 10.000s 20.305us 1 1 100.00
otbn_dmem_err 16.000s 40.019us 1 1 100.00
internal_integrity 1 4 25.00
otbn_alu_bignum_mod_err 27.000s 53.618us 1 1 100.00
otbn_controller_ispr_rdata_err 24.000s 230.363us 0 1 0.00
otbn_mac_bignum_acc_err 6.000s 30.225us 0 1 0.00
otbn_urnd_err 7.000s 106.348us 0 1 0.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 13.000s 19.078us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 7.000s 32.479us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 7.000s 29.996us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 933.000s 7059.739us 1 1 100.00
otbn_tl_intg_err 18.000s 229.338us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 48.000s 675.769us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 933.000s 7059.739us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 933.000s 7059.739us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 75.062us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 16.000s 40.019us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 10.000s 20.305us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 18.000s 229.338us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 18.000s 21.762us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 20.305us 1 1 100.00
otbn_dmem_err 16.000s 40.019us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 114.961us 1 1 100.00
otbn_illegal_mem_acc 13.000s 19.078us 1 1 100.00
otbn_sec_cm 933.000s 7059.739us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 933.000s 7059.739us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 14.000s 65.452us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 20.305us 1 1 100.00
otbn_dmem_err 16.000s 40.019us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 114.961us 1 1 100.00
otbn_illegal_mem_acc 13.000s 19.078us 1 1 100.00
otbn_sec_cm 933.000s 7059.739us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 933.000s 7059.739us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 18.000s 21.762us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 20.305us 1 1 100.00
otbn_dmem_err 16.000s 40.019us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 114.961us 1 1 100.00
otbn_illegal_mem_acc 13.000s 19.078us 1 1 100.00
otbn_sec_cm 933.000s 7059.739us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 933.000s 7059.739us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 14.000s 65.452us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 16.000s 46.894us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 147.871us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 51.000s 255.558us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 51.000s 255.558us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 11.000s 42.741us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 933.000s 7059.739us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 933.000s 7059.739us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 11.000s 64.971us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 933.000s 7059.739us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 933.000s 7059.739us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 18.000s 165.059us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 18.000s 165.059us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 10.000s 36.192us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 14.000s 65.452us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 14.000s 65.452us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 14.000s 65.452us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 47.000s 358.657us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 14.000s 65.452us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 14.000s 65.452us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 9.000s 52.000us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 14.000s 65.452us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 933.000s 7059.739us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 64.000s 320.080us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 23.075us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 2 test runs
otbn_controller_ispr_rdata_err 100625467917481183745935910801242976075391570865995493486927648053911398515809 107
UVM_INFO @ 230363366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_mac_bignum_acc_err 28362853636138407139731603098522210953752607980092204025492905329986654137163 111
UVM_INFO @ 30224748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 89972260019931783799002380828227563584778394397979765589009248536239003560004 251
UVM_INFO @ 320080211 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otbn_scoreboard.sv:321) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 1 test run
otbn_urnd_err 1480307301733409272845260679798147942934538766721545374134214695207773171385 111
UVM_INFO @ 106347581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---