Simulation Results: otp_ctrl

 
29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.92 %
  • code
  • 77.37 %
  • assert
  • 94.38 %
  • func
  • 71.02 %
  • line
  • 88.53 %
  • branch
  • 83.40 %
  • cond
  • 90.32 %
  • toggle
  • 80.16 %
  • FSM
  • 44.44 %
Validation stages
V1
100.00%
V2
95.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.330s 57.132us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.560s 3580.701us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.090s 1058.060us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.540s 46.137us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.440s 322.716us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.560s 111.490us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.620s 70.383us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.540s 46.137us 1 1 100.00
otp_ctrl_csr_aliasing 2.560s 111.490us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.290s 75.319us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.170s 45.605us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 13.590s 937.269us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.910s 209.029us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 16.410s 1709.164us 1 1 100.00
otp_ctrl_check_fail 18.310s 2876.897us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 3.680s 307.421us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 13.340s 1285.452us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 12.650s 7858.954us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 9.050s 2122.706us 1 1 100.00
otp_ctrl_parallel_lc_esc 15.680s 2031.910us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 14.740s 993.317us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 7.060s 4702.858us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 2.970s 2027.329us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 42.700s 14157.479us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.180s 45.799us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.730s 174.098us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.160s 182.498us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.160s 182.498us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.090s 1058.060us 1 1 100.00
otp_ctrl_csr_rw 1.540s 46.137us 1 1 100.00
otp_ctrl_csr_aliasing 2.560s 111.490us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.230s 135.800us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.090s 1058.060us 1 1 100.00
otp_ctrl_csr_rw 1.540s 46.137us 1 1 100.00
otp_ctrl_csr_aliasing 2.560s 111.490us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.230s 135.800us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
otp_ctrl_tl_intg_err 13.370s 3594.327us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 13.370s 3594.327us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.560s 3580.701us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.560s 3580.701us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 15.680s 2031.910us 1 1 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 15.680s 2031.910us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 15.680s 2031.910us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 15.680s 2031.910us 1 1 100.00
otp_ctrl_macro_errs 7.060s 4702.858us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 15.680s 2031.910us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 15.680s 2031.910us 1 1 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 15.680s 2031.910us 1 1 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 15.680s 2031.910us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 15.680s 2031.910us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 15.680s 2031.910us 1 1 100.00
otp_ctrl_macro_errs 7.060s 4702.858us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 15.680s 2031.910us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 15.680s 2031.910us 1 1 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.910s 209.029us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 18.310s 2876.897us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 13.340s 1285.452us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 13.340s 1285.452us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 13.340s 1285.452us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 13.340s 1285.452us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 13.340s 1285.452us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.560s 3580.701us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 13.340s 1285.452us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.560s 3580.701us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 118.590s 33682.144us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 3.680s 307.421us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.560s 3580.701us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.560s 3580.701us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 7.060s 4702.858us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 8.840s 3658.333us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.060s 26.325us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1208) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_macro_errs 2134639549305317205010807338243578082617107242281316936279426804854673629480 5164
UVM_INFO @ 4702857996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 90168039487881051236287278865093687101512342944963422535343044621817942136706 97
UVM_INFO @ 26325396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---