Simulation Results: pwrmgr

 
29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.86 %
  • code
  • 97.47 %
  • assert
  • 97.91 %
  • func
  • 98.19 %
  • line
  • 99.09 %
  • branch
  • 96.18 %
  • cond
  • 96.46 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.580s 40.901us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.660s 35.318us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.630s 23.999us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.060s 159.895us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.880s 45.318us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.960s 43.660us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.630s 23.999us 1 1 100.00
pwrmgr_csr_aliasing 0.880s 45.318us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.910s 163.262us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.910s 163.262us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.680s 24.944us 1 1 100.00
pwrmgr_lowpower_invalid 0.660s 56.207us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.810s 307.535us 1 1 100.00
pwrmgr_reset_invalid 0.840s 105.035us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.810s 307.535us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.730s 132.873us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.620s 33.307us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.740s 160.990us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 14.000s 11057.696us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.590s 54.197us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.470s 45.697us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.470s 45.697us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.660s 35.318us 1 1 100.00
pwrmgr_csr_rw 0.630s 23.999us 1 1 100.00
pwrmgr_csr_aliasing 0.880s 45.318us 1 1 100.00
pwrmgr_same_csr_outstanding 0.770s 200.339us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.660s 35.318us 1 1 100.00
pwrmgr_csr_rw 0.630s 23.999us 1 1 100.00
pwrmgr_csr_aliasing 0.880s 45.318us 1 1 100.00
pwrmgr_same_csr_outstanding 0.770s 200.339us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 1.230s 294.508us 1 1 100.00
pwrmgr_sec_cm 0.990s 378.322us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 0.990s 378.322us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 0.990s 378.322us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 1.230s 294.508us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.770s 720.753us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.730s 132.873us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.900s 721.722us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.760s 170.550us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.570s 38.742us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 0.990s 378.322us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 0.990s 378.322us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 0.990s 378.322us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.600s 81.168us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.570s 47.963us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.750s 488.256us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.630s 23.999us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.630s 23.999us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.690s 97.828us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 4.310s 5667.955us 1 1 100.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 16784382013757198892848268584581708230091059838729132145578811026142456493118 84
UVM_ERROR @ 97827991 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 97827991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 1 test run
pwrmgr_stress_all 18302201540300283306534946582119387028439478006986587219544810445949033003140 664
UVM_INFO @ 11057696332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---