Simulation Results: rstmgr

 
29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.66 %
  • code
  • 99.32 %
  • assert
  • 98.66 %
  • func
  • 98.01 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.61 %
  • toggle
  • 99.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.210s 268.915us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.800s 126.236us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.790s 77.772us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.530s 697.375us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 2.030s 424.824us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.080s 158.993us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.790s 77.772us 1 1 100.00
rstmgr_csr_aliasing 2.030s 424.824us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.760s 142.080us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.760s 465.027us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.980s 161.109us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.230s 976.793us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.230s 976.793us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.230s 976.793us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.230s 976.793us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 21.430s 7978.639us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.740s 80.111us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.600s 163.906us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.600s 163.906us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.800s 126.236us 1 1 100.00
rstmgr_csr_rw 0.790s 77.772us 1 1 100.00
rstmgr_csr_aliasing 2.030s 424.824us 1 1 100.00
rstmgr_same_csr_outstanding 0.950s 152.664us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.800s 126.236us 1 1 100.00
rstmgr_csr_rw 0.790s 77.772us 1 1 100.00
rstmgr_csr_aliasing 2.030s 424.824us 1 1 100.00
rstmgr_same_csr_outstanding 0.950s 152.664us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 9.510s 8566.968us 1 1 100.00
rstmgr_tl_intg_err 2.390s 1068.049us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 9.510s 8566.968us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 9.510s 8566.968us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.390s 1068.049us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.870s 115.531us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.280s 1412.663us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 0.930s 302.371us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 9.510s 8566.968us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.790s 77.772us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.790s 77.772us 1 1 100.00