Simulation Results: rv_timer

 
29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.61 %
  • code
  • 94.66 %
  • assert
  • 98.41 %
  • func
  • 96.76 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.610s 49.471us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.580s 28.468us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.590s 17.138us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.280s 684.093us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.650s 26.958us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.750s 91.199us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.590s 17.138us 1 1 100.00
rv_timer_csr_aliasing 0.650s 26.958us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.720s 176.119us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.390s 3097.329us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 3.350s 18064.098us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 3.350s 18064.098us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 0.970s 2797.292us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.520s 49.837us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.570s 63.416us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.770s 1731.360us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.770s 1731.360us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.580s 28.468us 1 1 100.00
rv_timer_csr_rw 0.590s 17.138us 1 1 100.00
rv_timer_csr_aliasing 0.650s 26.958us 1 1 100.00
rv_timer_same_csr_outstanding 0.710s 61.881us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.580s 28.468us 1 1 100.00
rv_timer_csr_rw 0.590s 17.138us 1 1 100.00
rv_timer_csr_aliasing 0.650s 26.958us 1 1 100.00
rv_timer_same_csr_outstanding 0.710s 61.881us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.700s 132.678us 1 1 100.00
rv_timer_tl_intg_err 0.770s 61.826us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.770s 61.826us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.880s 803.690us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 0.630s 150.097us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 19.090s 2355.288us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 108436300761291545951029711519485038629047194336469089004923617279999934300391 80
UVM_INFO @ 150096671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_random_reset 95059479394215513100791226883573518931878063773466687346578529775774323231617 81
UVM_INFO @ 176118740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---