Simulation Results: spi_host

 
29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.97 %
  • code
  • 91.14 %
  • assert
  • 95.27 %
  • func
  • 89.50 %
  • block
  • 96.78 %
  • line
  • 98.54 %
  • branch
  • 92.95 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 6.000s 978.242us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 47.147us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 65.859us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 162.952us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 28.921us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 83.425us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 65.859us 1 1 100.00
spi_host_csr_aliasing 1.000s 28.921us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 41.305us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 18.184us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 42.168us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 19.000s 1392.989us 1 1 100.00
spi_host_error_cmd 1.000s 32.967us 1 1 100.00
spi_host_event 4.000s 3726.881us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 96.272us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 96.272us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 96.272us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 59.000s 2803.997us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 3.000s 244.698us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 481.459us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 96.272us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 96.272us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 6.000s 978.242us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 6.000s 978.242us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 2.000s 81.499us 1 1 100.00
spien 1 1 100.00
spi_host_spien 4.000s 979.682us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 20.000s 2211.073us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 1558.646us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 19.000s 1392.989us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 16.357us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 22.092us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 157.385us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 157.385us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 47.147us 1 1 100.00
spi_host_csr_rw 2.000s 65.859us 1 1 100.00
spi_host_csr_aliasing 1.000s 28.921us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 70.835us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 47.147us 1 1 100.00
spi_host_csr_rw 2.000s 65.859us 1 1 100.00
spi_host_csr_aliasing 1.000s 28.921us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 70.835us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 196.353us 1 1 100.00
spi_host_sec_cm 1.000s 82.803us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 196.353us 1 1 100.00