Simulation Results: sram_ctrl/main

 
29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.13 %
  • code
  • 95.49 %
  • assert
  • 98.10 %
  • func
  • 91.80 %
  • block
  • 95.82 %
  • line
  • 96.45 %
  • branch
  • 93.67 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.000s 2941.594us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 38.045us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 24.672us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 218.428us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 38.231us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 354.800us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 24.672us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 38.231us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 203.000s 23162.072us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 78.000s 10007.902us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 12.000s 4891.921us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 77.000s 8981.918us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 137.000s 63130.189us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 56.000s 29850.453us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 16.000s 10012.132us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 16.000s 16545.728us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 718.946us 1 1 100.00
sram_ctrl_partial_access_b2b 206.000s 109350.505us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 3.000s 658.936us 0 1 0.00
sram_ctrl_throughput_w_partial_write 4.000s 2759.021us 0 1 0.00
sram_ctrl_throughput_w_readback 4.000s 684.852us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 13.000s 22693.142us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 1337.170us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 61.000s 72146.961us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 38.082us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 315.575us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 315.575us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 38.045us 1 1 100.00
sram_ctrl_csr_rw 1.000s 24.672us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 38.231us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 56.029us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 38.045us 1 1 100.00
sram_ctrl_csr_rw 1.000s 24.672us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 38.231us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 56.029us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 12.000s 3711.390us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 808.019us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 208.385us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 808.019us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 208.385us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 13.000s 22693.142us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 13.000s 22693.142us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 24.672us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 16.000s 16545.728us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 16.000s 16545.728us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 16.000s 16545.728us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 16.000s 10012.132us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.000s 695.534us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 12.000s 3711.390us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.000s 3917.132us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 2941.594us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 2941.594us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 16.000s 16545.728us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 808.019us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 16.000s 10012.132us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 808.019us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 808.019us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.000s 2941.594us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 808.019us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 13.000s 748.508us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 46534545450818644633459496692619377262077137264614038659748114496874553544209 86
UVM_INFO @ 658936116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 63369645374044145428758210095816061598797454937285423748036984534049191953764 86
UVM_INFO @ 2759020707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 99236394006233320335326756775297045655159885815150170902118028475225993846785 86
UVM_INFO @ 684851816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---