Simulation Results: sram_ctrl/ret

 
29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.44 %
  • code
  • 82.39 %
  • assert
  • 97.94 %
  • func
  • 91.00 %
  • block
  • 93.88 %
  • line
  • 94.98 %
  • branch
  • 89.64 %
  • toggle
  • 78.28 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 287.252us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 55.950us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.594us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 3.000s 367.330us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 84.243us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 65.874us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 14.594us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 84.243us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 5.000s 391.493us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 5.000s 201.819us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 5.000s 369.937us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 122.000s 10763.663us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 4.000s 147.033us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 14.000s 1094.019us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.000s 3664.399us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 3.000s 440.893us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 1.000s 139.245us 1 1 100.00
sram_ctrl_partial_access_b2b 152.000s 44251.655us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 1.000s 64.877us 0 1 0.00
sram_ctrl_throughput_w_partial_write 1.000s 43.998us 0 1 0.00
sram_ctrl_throughput_w_readback 2.000s 256.338us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 3.000s 106.354us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 32.291us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 32.000s 14019.675us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 12.197us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 74.794us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 74.794us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 55.950us 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.594us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 84.243us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 145.562us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 55.950us 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.594us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 84.243us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 145.562us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 233.013us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 722.741us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 147.663us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 722.741us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 147.663us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 106.354us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 3.000s 106.354us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.594us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 3.000s 440.893us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 3.000s 440.893us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 3.000s 440.893us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.000s 3664.399us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 155.371us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 233.013us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 119.385us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 287.252us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 287.252us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 3.000s 440.893us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 722.741us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.000s 3664.399us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 722.741us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 722.741us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 287.252us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 722.741us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 20.000s 4435.310us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 60221987931333719056460860944989936279527668510049295564470134468283954429476 86
UVM_INFO @ 64877302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 73164261491267243740268996232168732542974332849107484274092564690709388239343 86
UVM_INFO @ 43997869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 55009683649434798082708547536310088773139521698676806261037078931664986737027 86
UVM_INFO @ 256338315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---