Simulation Results: sysrst_ctrl

 
29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.20 %
  • code
  • 92.24 %
  • assert
  • 92.53 %
  • func
  • 64.84 %
  • line
  • 96.72 %
  • branch
  • 97.11 %
  • cond
  • 94.28 %
  • toggle
  • 100.00 %
  • FSM
  • 73.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.220s 2135.969us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 3.890s 2468.839us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 4.850s 2433.198us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.700s 2544.180us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 10.070s 6040.342us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.320s 2059.566us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 6.060s 6149.035us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 2.490s 2717.027us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 1.620s 2106.005us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.320s 2059.566us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.490s 2717.027us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 119.490s 70348.680us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 9.280s 43310.183us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 1.570s 3679.851us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.840s 3839.649us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 2.690s 2521.599us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 3.880s 2119.112us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 8.750s 5158.125us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 5.220s 2610.559us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 1.340s 12526.191us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 25.080s 31156.900us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 5.980s 15481.725us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 2.260s 2022.119us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.840s 2038.171us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 3.440s 2324.459us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 3.440s 2324.459us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 10.070s 6040.342us 1 1 100.00
sysrst_ctrl_csr_rw 4.320s 2059.566us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.490s 2717.027us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 11.970s 5259.963us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 10.070s 6040.342us 1 1 100.00
sysrst_ctrl_csr_rw 4.320s 2059.566us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.490s 2717.027us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 11.970s 5259.963us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 32.280s 42058.641us 1 1 100.00
sysrst_ctrl_tl_intg_err 21.360s 42876.571us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 21.360s 42876.571us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 8.160s 8751.084us 1 1 100.00