Simulation Results: uart

 
29/07/2026 15:30:30 DVSim: v1.50.0 sha: 5af475c json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.13 %
  • code
  • 96.14 %
  • assert
  • 98.85 %
  • func
  • 54.40 %
  • line
  • 99.17 %
  • branch
  • 97.20 %
  • cond
  • 96.62 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 0.870s 147.585us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.690s 57.830us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.600s 36.971us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.060s 311.145us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.790s 31.959us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.790s 65.944us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.600s 36.971us 1 1 100.00
uart_csr_aliasing 0.790s 31.959us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 102.270s 125608.231us 1 1 100.00
parity 2 2 100.00
uart_smoke 0.870s 147.585us 1 1 100.00
uart_tx_rx 102.270s 125608.231us 1 1 100.00
parity_error 2 2 100.00
uart_intr 13.620s 22500.265us 1 1 100.00
uart_rx_parity_err 125.780s 150395.661us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 102.270s 125608.231us 1 1 100.00
uart_intr 13.620s 22500.265us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 7.650s 9158.125us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 39.340s 49854.832us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 5.300s 8733.040us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 13.620s 22500.265us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 13.620s 22500.265us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 13.620s 22500.265us 1 1 100.00
perf 1 1 100.00
uart_perf 62.910s 21993.831us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 7.140s 6277.314us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 7.140s 6277.314us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 105.270s 63056.179us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.760s 3651.842us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.320s 1967.228us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 4.930s 5378.329us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 73.900s 92678.091us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 148.640s 29604.450us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.550s 14.055us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.680s 80.144us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.210s 216.071us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.210s 216.071us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.690s 57.830us 1 1 100.00
uart_csr_rw 0.600s 36.971us 1 1 100.00
uart_csr_aliasing 0.790s 31.959us 1 1 100.00
uart_same_csr_outstanding 0.750s 94.251us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.690s 57.830us 1 1 100.00
uart_csr_rw 0.600s 36.971us 1 1 100.00
uart_csr_aliasing 0.790s 31.959us 1 1 100.00
uart_same_csr_outstanding 0.750s 94.251us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.790s 117.557us 1 1 100.00
uart_tl_intg_err 0.890s 307.381us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.890s 307.381us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 37.270s 3754.375us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 1 test run
uart_noise_filter 71842735654009041385377424925267367508019686945445582388510176523848160240745 85
UVM_ERROR @ 61954348805 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 61954348805 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 62009168805 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 3, clk_pulses: 0
UVM_ERROR @ 62009308805 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (248 [0xf8] vs 254 [0xfe]) reg name: uart_reg_block.rdata