Simulation Results: adc_ctrl

 
30/07/2026 15:30:28 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.74 %
  • code
  • 92.21 %
  • assert
  • 92.06 %
  • func
  • 12.94 %
  • line
  • 97.97 %
  • branch
  • 96.23 %
  • cond
  • 86.02 %
  • toggle
  • 99.76 %
  • FSM
  • 81.08 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 2.590s 5760.357us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.150s 880.417us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.340s 501.065us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 62.560s 42972.694us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 3.070s 1286.319us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.640s 601.289us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.340s 501.065us 1 1 100.00
adc_ctrl_csr_aliasing 3.070s 1286.319us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 0.680s 283.362us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.820s 311.850us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.850s 418.981us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.930s 420.096us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.760s 481.949us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.720s 435.430us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.990s 296.714us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 1.280s 517.581us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 6.500s 4273.821us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 3.820s 43975.438us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 109.350s 85169.428us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 24.660s 70759.144us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.710s 391.479us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.040s 536.429us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.870s 1016.120us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.870s 1016.120us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.150s 880.417us 1 1 100.00
adc_ctrl_csr_rw 1.340s 501.065us 1 1 100.00
adc_ctrl_csr_aliasing 3.070s 1286.319us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.010s 1894.921us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.150s 880.417us 1 1 100.00
adc_ctrl_csr_rw 1.340s 501.065us 1 1 100.00
adc_ctrl_csr_aliasing 3.070s 1286.319us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.010s 1894.921us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 11.620s 8511.358us 1 1 100.00
adc_ctrl_tl_intg_err 2.930s 4820.819us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 2.930s 4820.819us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 4.650s 2942.658us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 67443812405716539602174955730558877001166699363090416092501511564963334607060 386
UVM_INFO @ 283362028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 20718119058801327035857710878494084728586676927383414258151261096084982070136 386
UVM_INFO @ 311849526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 8301052864114750552667161973569278362405681857770689554584513990913837414138 386
UVM_INFO @ 418980567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 37722414437250090340119822439280074641617636975314485154215400993000471869062 386
UVM_INFO @ 420095653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 76252818685724801325904569122191808042723247370813126477080916362396338817512 386
UVM_INFO @ 481948928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 49997764428087559535862473164276427636445682176524011262614090749150247664195 386
UVM_INFO @ 435430369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 33940303155359092090057615614180431264549399035356826921324472732055892428711 386
UVM_INFO @ 517581129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 54913336800253147990870057245395005147017739335019859104731406995204706805105 386
UVM_INFO @ 296713970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 51286714127242414757424138790503822727259870890808953603267005244254031280098 450
UVM_INFO @ 2942658248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 34713950804601038489202920074439797200965468425676180741808566621234501024321 561
UVM_INFO @ 70759144270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---