Simulation Results: aes/masked

 
30/07/2026 15:30:28 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.02 %
  • code
  • 94.27 %
  • assert
  • 98.23 %
  • func
  • 74.57 %
  • block
  • 94.40 %
  • line
  • 96.02 %
  • branch
  • 87.52 %
  • toggle
  • 97.99 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
94.12%
V2S
93.75%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 69.179us 1 1 100.00
smoke 1 1 100.00
aes_smoke 6.000s 844.994us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 794.128us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 109.424us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 1735.978us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 139.997us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 78.672us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 109.424us 1 1 100.00
aes_csr_aliasing 2.000s 139.997us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 6.000s 844.994us 1 1 100.00
aes_config_error 3.000s 189.511us 1 1 100.00
aes_stress 3.000s 228.194us 1 1 100.00
key_length 3 3 100.00
aes_smoke 6.000s 844.994us 1 1 100.00
aes_config_error 3.000s 189.511us 1 1 100.00
aes_stress 3.000s 228.194us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 228.194us 1 1 100.00
aes_b2b 13.000s 348.230us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 228.194us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 6.000s 844.994us 1 1 100.00
aes_config_error 3.000s 189.511us 1 1 100.00
aes_stress 3.000s 228.194us 1 1 100.00
aes_alert_reset 5.000s 576.509us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 71.989us 1 1 100.00
aes_config_error 3.000s 189.511us 1 1 100.00
aes_alert_reset 5.000s 576.509us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 73.728us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 325.164us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 5.000s 576.509us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 228.194us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 228.194us 1 1 100.00
aes_sideload 3.000s 71.522us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 4.000s 190.418us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 14.000s 770.572us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 57.523us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 233.900us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 233.900us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 794.128us 1 1 100.00
aes_csr_rw 2.000s 109.424us 1 1 100.00
aes_csr_aliasing 2.000s 139.997us 1 1 100.00
aes_same_csr_outstanding 1.000s 83.359us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 794.128us 1 1 100.00
aes_csr_rw 2.000s 109.424us 1 1 100.00
aes_csr_aliasing 2.000s 139.997us 1 1 100.00
aes_same_csr_outstanding 1.000s 83.359us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 181.272us 1 1 100.00
fault_inject 2 3 66.67
aes_fi 3.000s 218.943us 0 1 0.00
aes_control_fi 2.000s 52.123us 1 1 100.00
aes_cipher_fi 4.000s 85.104us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 160.884us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 160.884us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 160.884us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 160.884us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 323.200us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 3098.148us 1 1 100.00
aes_tl_intg_err 2.000s 405.267us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 405.267us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 5.000s 576.509us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 160.884us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 160.884us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 6.000s 844.994us 1 1 100.00
aes_stress 3.000s 228.194us 1 1 100.00
aes_alert_reset 5.000s 576.509us 1 1 100.00
aes_core_fi 2.000s 214.482us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 189.511us 1 1 100.00
aes_stress 3.000s 228.194us 1 1 100.00
aes_core_fi 2.000s 214.482us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 160.884us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 81.012us 1 1 100.00
aes_stress 3.000s 228.194us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 228.194us 1 1 100.00
aes_sideload 3.000s 71.522us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 81.012us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 81.012us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 81.012us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 81.012us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 81.012us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 228.194us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 228.194us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 218.943us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 3.000s 218.943us 0 1 0.00
aes_control_fi 2.000s 52.123us 1 1 100.00
aes_cipher_fi 4.000s 85.104us 1 1 100.00
aes_ctr_fi 2.000s 48.774us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 218.943us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 3.000s 218.943us 0 1 0.00
aes_control_fi 2.000s 52.123us 1 1 100.00
aes_cipher_fi 4.000s 85.104us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 4.000s 85.104us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 218.943us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 218.943us 0 1 0.00
aes_control_fi 2.000s 52.123us 1 1 100.00
aes_ctr_fi 2.000s 48.774us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 218.943us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 3.000s 218.943us 0 1 0.00
aes_control_fi 2.000s 52.123us 1 1 100.00
aes_cipher_fi 4.000s 85.104us 1 1 100.00
aes_ctr_fi 2.000s 48.774us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 5.000s 576.509us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 3.000s 218.943us 0 1 0.00
aes_control_fi 2.000s 52.123us 1 1 100.00
aes_cipher_fi 4.000s 85.104us 1 1 100.00
aes_ctr_fi 2.000s 48.774us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 3.000s 218.943us 0 1 0.00
aes_control_fi 2.000s 52.123us 1 1 100.00
aes_cipher_fi 4.000s 85.104us 1 1 100.00
aes_ctr_fi 2.000s 48.774us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 218.943us 0 1 0.00
aes_control_fi 2.000s 52.123us 1 1 100.00
aes_ctr_fi 2.000s 48.774us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 218.943us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 3.000s 218.943us 0 1 0.00
aes_control_fi 2.000s 52.123us 1 1 100.00
aes_cipher_fi 4.000s 85.104us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 22.000s 725.165us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 9214875089741808722044916012962827558272697742606453224460625751217528299300 5317
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0
UVM_FATAL (aes_scoreboard.sv:785) scoreboard [scoreboard] # * 1 test run
aes_stress_all 5151704208921194673093938930287549797884051439891038555063304613230901549325 24462
TEST FAILED MESSAGES DID NOT MATCH
0 c1 22 22 0
1 00 3d 3d 0
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all_with_rand_reset 36448633246905355508521240471305702975456321498963808393840155667961229666455 816
UVM_INFO @ 725164861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---