Simulation Results: chip

 
30/07/2026 15:30:28 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.73 %
  • code
  • 81.56 %
  • assert
  • 97.49 %
  • func
  • 48.14 %
  • line
  • 94.20 %
  • branch
  • 93.80 %
  • cond
  • 89.03 %
  • toggle
  • 73.65 %
  • FSM
  • 57.14 %
Validation stages
V1
94.44%
V2
73.65%
V2S
100.00%
V3
61.54%
unmapped
63.64%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 163.700s 3705.396us 1 1 100.00
chip_sw_example_rom 79.860s 2485.605us 1 1 100.00
chip_sw_example_manufacturer 165.850s 3798.675us 1 1 100.00
chip_sw_example_concurrency 173.200s 3638.167us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 182.790s 5968.793us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 232.730s 4275.277us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 513.560s 7196.481us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4099.850s 36083.314us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 73.690s 2542.291us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4099.850s 36083.314us 1 1 100.00
chip_csr_rw 232.730s 4275.277us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 4.020s 38.718us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 304.160s 4923.609us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 304.160s 4923.609us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 304.160s 4923.609us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 353.210s 4511.368us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 353.210s 4511.368us 1 1 100.00
chip_sw_uart_tx_rx_idx1 316.370s 4155.896us 1 1 100.00
chip_sw_uart_tx_rx_idx2 349.890s 4818.658us 1 1 100.00
chip_sw_uart_tx_rx_idx3 328.080s 4832.798us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 370.170s 5520.480us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 393.490s 5493.140us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 247.310s 4619.110us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 169.060s 5060.306us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 169.060s 5060.306us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 149.380s 3014.635us 1 1 100.00
chip_sw_sleep_pin_wake 0 1 0.00
chip_sw_sleep_pin_wake 150.470s 3444.759us 0 1 0.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 165.750s 4399.280us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 88.750s 2663.760us 1 1 100.00
chip_tap_straps_testunlock0 383.160s 8022.023us 1 1 100.00
chip_tap_straps_rma 298.340s 5923.555us 1 1 100.00
chip_tap_straps_prod 104.720s 2854.695us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 516.290s 7092.981us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 516.290s 7092.981us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 681.290s 9093.663us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 953.770s 11593.012us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 379.020s 4755.621us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 544.410s 6449.852us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4020.180s 19347.738us 1 1 100.00
chip_sw_aes_enc_jitter_en 203.780s 4130.194us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 518.390s 6628.985us 1 1 100.00
chip_sw_hmac_enc_jitter_en 144.620s 3061.902us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 683.350s 8706.121us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 204.640s 3514.760us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 364.620s 4949.853us 1 1 100.00
chip_sw_clkmgr_jitter 183.710s 3993.129us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 200.080s 3369.435us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 300.670s 5865.620us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 220.810s 5392.307us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 178.470s 3484.280us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 220.810s 5392.307us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 149.670s 3055.392us 1 1 100.00
chip_sw_aes_smoketest 185.340s 3760.470us 1 1 100.00
chip_sw_aon_timer_smoketest 189.300s 3478.302us 1 1 100.00
chip_sw_clkmgr_smoketest 132.740s 3670.118us 1 1 100.00
chip_sw_csrng_smoketest 222.050s 3564.114us 1 1 100.00
chip_sw_entropy_src_smoketest 1025.710s 8214.132us 1 1 100.00
chip_sw_gpio_smoketest 189.480s 3631.947us 1 1 100.00
chip_sw_hmac_smoketest 261.700s 4195.700us 1 1 100.00
chip_sw_kmac_smoketest 228.570s 3801.245us 1 1 100.00
chip_sw_otbn_smoketest 738.740s 7478.403us 1 1 100.00
chip_sw_pwrmgr_smoketest 329.520s 6962.775us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 250.150s 7454.927us 1 1 100.00
chip_sw_rv_plic_smoketest 134.670s 3240.497us 1 1 100.00
chip_sw_rv_timer_smoketest 154.580s 3061.001us 1 1 100.00
chip_sw_rstmgr_smoketest 140.110s 4023.133us 1 1 100.00
chip_sw_sram_ctrl_smoketest 148.000s 3207.114us 1 1 100.00
chip_sw_uart_smoketest 149.220s 3682.052us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 136.210s 3720.206us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 359.780s 7420.953us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7572.550s 62081.574us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3125.150s 15797.017us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 94.890s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 913.910s 15285.595us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 497.480s 15537.867us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7234.560s 55674.300us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7672.710s 58119.674us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 161.940s 4294.236us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 161.940s 4294.236us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4099.850s 36083.314us 1 1 100.00
chip_same_csr_outstanding 2911.630s 30514.318us 1 1 100.00
chip_csr_hw_reset 182.790s 5968.793us 1 1 100.00
chip_csr_rw 232.730s 4275.277us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4099.850s 36083.314us 1 1 100.00
chip_same_csr_outstanding 2911.630s 30514.318us 1 1 100.00
chip_csr_hw_reset 182.790s 5968.793us 1 1 100.00
chip_csr_rw 232.730s 4275.277us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 13.770s 200.335us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.100s 43.172us 1 1 100.00
xbar_smoke_large_delays 43.710s 8113.223us 1 1 100.00
xbar_smoke_slow_rsp 31.830s 3876.773us 1 1 100.00
xbar_random_zero_delays 30.030s 549.417us 1 1 100.00
xbar_random_large_delays 171.980s 31359.379us 1 1 100.00
xbar_random_slow_rsp 131.620s 15448.251us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 13.140s 166.104us 1 1 100.00
xbar_error_and_unmapped_addr 7.730s 177.901us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 10.580s 378.553us 1 1 100.00
xbar_error_and_unmapped_addr 7.730s 177.901us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 63.430s 2090.316us 1 1 100.00
xbar_access_same_device_slow_rsp 564.250s 64728.890us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 18.570s 357.321us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 503.330s 21931.598us 1 1 100.00
xbar_stress_all_with_error 63.190s 1255.249us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 158.910s 1223.331us 1 1 100.00
xbar_stress_all_with_reset_error 257.530s 5630.386us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3125.150s 15797.017us 1 1 100.00
rom_e2e_shutdown_output 0 1 0.00
rom_e2e_shutdown_output 452.280s 10533.303us 0 1 0.00
rom_e2e_shutdown_exception_c 0 1 0.00
rom_e2e_shutdown_exception_c 417.940s 5920.088us 0 1 0.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 40.486s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 8.084s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 22.233s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 27.639s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 22.985s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 40.822s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 29.226s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 8.703s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 32.215s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 8.548s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 160.523s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 49.220s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 21.288s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 65.392s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 65.905s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 19.160s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 25.990s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 18.670s 10.400us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 21.200s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 19.910s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 19.670s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 19.890s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 19.150s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 24.050s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 20.320s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 21.340s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 20.620s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 21.590s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 20.740s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 19.490s 10.400us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 56.352s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 66.559s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 104.559s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 64.857s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 47.830s 0.000us 0 1 0.00
rom_e2e_keymgr_init 1 3 33.33
rom_e2e_keymgr_init_rom_ext_meas 3077.530s 17138.324us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_no_meas 5897.980s 30630.269us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 3129.940s 16611.545us 0 1 0.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3095.910s 15831.675us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2797.580s 35766.814us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2797.580s 35766.814us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 209.800s 3538.234us 1 1 100.00
chip_sw_aes_enc_jitter_en 203.780s 4130.194us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 221.500s 4177.717us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 127.880s 2635.313us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1363.320s 11452.514us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 244.690s 4550.624us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 319.580s 5230.530us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 445.740s 7293.405us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 452.740s 5940.390us 1 1 100.00
chip_plic_all_irqs_10 259.020s 4162.871us 1 1 100.00
chip_plic_all_irqs_20 335.380s 4213.274us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 194.180s 3979.638us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1161.740s 14760.699us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 228.400s 4897.994us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 152.010s 2856.688us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 14400.171s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1019.560s 8316.898us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1069.680s 8939.786us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 776.320s 7950.374us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8478.820s 256189.174us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 260.840s 4051.183us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 329.520s 6962.775us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 260.840s 4051.183us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 406.680s 8178.005us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 406.680s 8178.005us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 400.710s 8174.554us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 319.230s 5657.365us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 532.570s 6711.933us 1 1 100.00
chip_sw_aes_idle 127.880s 2635.313us 1 1 100.00
chip_sw_hmac_enc_idle 144.310s 3301.842us 1 1 100.00
chip_sw_kmac_idle 190.830s 3165.558us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 352.570s 5056.847us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 398.470s 5542.254us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 283.960s 5855.840us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 404.570s 6061.666us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 856.000s 11109.905us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 389.840s 4264.043us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 399.510s 5855.451us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 404.300s 4227.686us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 441.740s 5966.985us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 396.330s 4648.694us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 417.760s 5844.790us 1 1 100.00
chip_sw_ast_clk_outputs 681.290s 9093.663us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 329.990s 6333.991us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 404.300s 4227.686us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 441.740s 5966.985us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 379.020s 4755.621us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 544.410s 6449.852us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4020.180s 19347.738us 1 1 100.00
chip_sw_aes_enc_jitter_en 203.780s 4130.194us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 518.390s 6628.985us 1 1 100.00
chip_sw_hmac_enc_jitter_en 144.620s 3061.902us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 683.350s 8706.121us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 204.640s 3514.760us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 364.620s 4949.853us 1 1 100.00
chip_sw_clkmgr_jitter 183.710s 3993.129us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 153.990s 3731.009us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 413.780s 5245.078us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 584.420s 7258.061us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3949.740s 25052.542us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 146.850s 3376.602us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 182.290s 3441.839us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 582.340s 10036.591us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 187.730s 3969.836us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 313.850s 6092.214us 1 1 100.00
chip_sw_flash_init_reduced_freq 1359.630s 27347.015us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 3090.090s 24807.216us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 681.290s 9093.663us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 365.970s 5338.203us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 277.700s 4490.135us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 445.740s 7293.405us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1019.560s 8316.898us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 1944.440s 25722.120us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 278.080s 5387.780us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 495.240s 7430.364us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 200.920s 3633.043us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 4306.870s 24735.466us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 160.270s 3106.725us 1 1 100.00
chip_sw_edn_entropy_reqs 590.330s 6943.943us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 160.270s 3106.725us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 1944.440s 25722.120us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 175.150s 3611.555us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1512.660s 31549.602us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 595.960s 6276.003us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 544.410s 6449.852us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 336.420s 3759.954us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 379.020s 4755.621us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3022.170s 45039.745us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1512.660s 31549.602us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 242.540s 4183.791us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1268.170s 12031.096us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 197.890s 4292.578us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3022.170s 45039.745us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 197.890s 4292.578us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 197.890s 4292.578us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 197.890s 4292.578us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 197.890s 4292.578us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 445.740s 7293.405us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 379.250s 12322.190us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 521.170s 5149.673us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 470.030s 6767.151us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 470.030s 6767.151us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 158.770s 2822.731us 1 1 100.00
chip_sw_hmac_enc_jitter_en 144.620s 3061.902us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 144.310s 3301.842us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 972.170s 8714.796us 1 1 100.00
chip_sw_hmac_multistream_mode 0 1 0.00
chip_sw_hmac_multistream 1531.010s 12018.537us 0 1 0.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 364.720s 5125.772us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 405.290s 4934.230us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 393.920s 5335.426us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 254.550s 4674.915us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1268.170s 12031.096us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 683.350s 8706.121us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1206.070s 11113.683us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1363.320s 11452.514us 1 1 100.00
chip_sw_keymgr_sideload_otbn 0 1 0.00
chip_sw_keymgr_sideload_otbn 4006.340s 20026.687us 0 1 0.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 148.470s 3765.230us 1 1 100.00
chip_sw_kmac_mode_kmac 156.550s 3242.731us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 204.640s 3514.760us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1268.170s 12031.096us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 620.520s 13495.488us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 140.730s 3061.502us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 927.700s 7949.581us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 190.830s 3165.558us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 319.580s 5230.530us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 88.750s 2663.760us 1 1 100.00
chip_tap_straps_rma 298.340s 5923.555us 1 1 100.00
chip_tap_straps_prod 104.720s 2854.695us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 123.150s 2559.659us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 620.520s 13495.488us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 620.520s 13495.488us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 620.520s 13495.488us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1487.750s 13991.814us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 197.890s 4292.578us 0 1 0.00
chip_sw_flash_rma_unlocked 3022.170s 45039.745us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 224.020s 4383.471us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 507.140s 9425.113us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 546.770s 7826.736us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 541.770s 10014.461us 0 1 0.00
chip_sw_lc_ctrl_transition 620.520s 13495.488us 1 1 100.00
chip_sw_keymgr_key_derivation 1268.170s 12031.096us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 340.160s 10051.357us 1 1 100.00
chip_sw_sram_ctrl_execution_main 553.330s 9954.295us 1 1 100.00
chip_prim_tl_access 379.250s 12322.190us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 329.990s 6333.991us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 389.840s 4264.043us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 399.510s 5855.451us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 404.300s 4227.686us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 441.740s 5966.985us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 396.330s 4648.694us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 417.760s 5844.790us 1 1 100.00
chip_tap_straps_dev 88.750s 2663.760us 1 1 100.00
chip_tap_straps_rma 298.340s 5923.555us 1 1 100.00
chip_tap_straps_prod 104.720s 2854.695us 1 1 100.00
chip_rv_dm_lc_disabled 64.250s 3252.952us 0 1 0.00
chip_lc_scrap 3 4 75.00
chip_sw_lc_ctrl_rma_to_scrap 171.910s 4423.899us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 658.360s 27270.102us 0 1 0.00
chip_sw_lc_ctrl_test_locked0_to_scrap 78.440s 3155.014us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 98.520s 4166.645us 1 1 100.00
chip_lc_test_locked 0 2 0.00
chip_sw_lc_walkthrough_testunlocks 953.290s 35334.837us 0 1 0.00
chip_rv_dm_lc_disabled 64.250s 3252.952us 0 1 0.00
chip_sw_lc_walkthrough 1 5 20.00
chip_sw_lc_walkthrough_dev 695.470s 9334.148us 0 1 0.00
chip_sw_lc_walkthrough_prod 761.000s 10789.088us 0 1 0.00
chip_sw_lc_walkthrough_prodend 525.520s 10048.118us 1 1 100.00
chip_sw_lc_walkthrough_rma 448.490s 7940.980us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 953.290s 35334.837us 0 1 0.00
chip_sw_lc_ctrl_volatile_raw_unlock 1 3 33.33
chip_sw_lc_ctrl_volatile_raw_unlock 88.150s 2859.346us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 69.360s 3104.366us 0 1 0.00
rom_volatile_raw_unlock 25.465s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3964.180s 16828.459us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 4020.180s 19347.738us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 532.570s 6711.933us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 532.570s 6711.933us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 532.570s 6711.933us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 279.020s 4843.856us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 620.520s 13495.488us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1512.660s 31549.602us 1 1 100.00
chip_sw_otbn_mem_scramble 279.020s 4843.856us 1 1 100.00
chip_sw_keymgr_key_derivation 1268.170s 12031.096us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 301.650s 5075.191us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 163.240s 2993.393us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1512.660s 31549.602us 1 1 100.00
chip_sw_otbn_mem_scramble 279.020s 4843.856us 1 1 100.00
chip_sw_keymgr_key_derivation 1268.170s 12031.096us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 301.650s 5075.191us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 163.240s 2993.393us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 620.520s 13495.488us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 326.740s 5499.280us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 123.150s 2559.659us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 224.020s 4383.471us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 507.140s 9425.113us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 546.770s 7826.736us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 541.770s 10014.461us 0 1 0.00
chip_sw_lc_ctrl_transition 620.520s 13495.488us 1 1 100.00
chip_prim_tl_access 379.250s 12322.190us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 379.250s 12322.190us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 772.890s 8532.751us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 153.610s 5665.427us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 950.160s 29877.838us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 273.960s 7546.032us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 333.680s 7622.172us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 346.530s 9118.824us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 808.690s 29477.350us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 269.080s 7012.987us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 406.680s 8178.005us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 955.700s 14624.945us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 294.330s 6334.960us 1 1 100.00
chip_sw_pwrmgr_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_full_aon_reset 153.610s 5665.427us 0 1 0.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 296.540s 5246.891us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 556.270s 11708.465us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 359.530s 8791.828us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 153.930s 4265.732us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 218.690s 6354.791us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 575.330s 10014.873us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1117.580s 15876.582us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1768.600s 36580.092us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 162.870s 3240.217us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 445.740s 7293.405us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 340.160s 10051.357us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 340.160s 10051.357us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 1117.580s 15876.582us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 218.690s 6354.791us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 294.330s 6334.960us 1 1 100.00
chip_sw_pwrmgr_smoketest 329.520s 6962.775us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 210.510s 4432.111us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 362.650s 7319.389us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 193.680s 4137.106us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1161.740s 14760.699us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 133.030s 2943.922us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 445.740s 7293.405us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1069.680s 8939.786us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 454.460s 5410.059us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 412.240s 5491.101us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 204.650s 4564.925us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 163.240s 2993.393us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 362.650s 7319.389us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 362.650s 7319.389us 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 1 1 100.00
chip_sw_rv_core_ibex_mcounteren_writable 172.050s 3569.585us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 963.590s 17101.228us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 1053.350s 16624.746us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 210.510s 4432.111us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 209.890s 4079.300us 0 1 0.00
chip_rv_dm_access_after_wakeup 0 1 0.00
chip_sw_rv_dm_access_after_wakeup 1156.330s 14193.193us 0 1 0.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 298.340s 5923.555us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 64.250s 3252.952us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 452.740s 5940.390us 1 1 100.00
chip_plic_all_irqs_10 259.020s 4162.871us 1 1 100.00
chip_plic_all_irqs_20 335.380s 4213.274us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 162.470s 3904.469us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 171.450s 3697.556us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3125.150s 15797.017us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 204.290s 4115.302us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 181.430s 2839.114us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 218.260s 4215.972us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 184.370s 3641.670us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 301.650s 5075.191us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 364.620s 4949.853us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 527.990s 9543.438us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 425.810s 9027.858us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 553.330s 9954.295us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 445.740s 7293.405us 1 1 100.00
chip_sw_data_integrity_escalation 516.290s 7092.981us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1 2 50.00
chip_sw_pwrmgr_sysrst_ctrl_reset 575.330s 10014.873us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1001.820s 25225.676us 0 1 0.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 167.040s 3208.633us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 224.000s 4020.922us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 300.780s 5685.700us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 0 1 0.00
chip_sw_sysrst_ctrl_reset 1001.820s 25225.676us 0 1 0.00
chip_sw_sysrst_ctrl_sleep_reset 0 1 0.00
chip_sw_sysrst_ctrl_reset 1001.820s 25225.676us 0 1 0.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2149.160s 20931.516us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2149.160s 20931.516us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 305.300s 5928.133us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2797.580s 35766.814us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 173.580s 3907.836us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 193.960s 3598.260us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 243.710s 4281.017us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 328.610s 4729.892us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 935.030s 8667.016us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5020.500s 31736.445us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1790.400s 13396.270us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 194.780s 3611.798us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 185.890s 3451.515us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 117.930s 3157.173us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9722.920s 69576.417us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1119.360s 7267.308us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 202.300s 5268.856us 0 1 0.00
rom_e2e_jtag_debug_dev 241.610s 4955.518us 0 1 0.00
rom_e2e_jtag_debug_rma 208.920s 3911.920us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 99.400s 3463.036us 0 1 0.00
rom_e2e_jtag_inject_dev 74.530s 2891.940us 0 1 0.00
rom_e2e_jtag_inject_rma 77.820s 2582.725us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 39.295s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 264.650s 4227.041us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 309.870s 3567.851us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 470.370s 4910.771us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 822.310s 7458.421us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 260.590s 3014.646us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 603.530s 5779.959us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 67.490s 2894.160us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 180.300s 3232.004us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 287.250s 6725.828us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 234.890s 5005.098us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1117.580s 15876.582us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 202.300s 5268.856us 0 1 0.00
rom_e2e_jtag_debug_dev 241.610s 4955.518us 0 1 0.00
rom_e2e_jtag_debug_rma 208.920s 3911.920us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 0 1 0.00
chip_sw_rv_dm_access_after_escalation_reset 200.120s 3481.683us 0 1 0.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 445.740s 7293.405us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5533.660s 38606.829us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5533.660s 38606.829us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 170.870s 4457.136us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 353.210s 4511.368us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 2977.820s 19661.433us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 11 63.64
chip_sival_flash_info_access 237.430s 3671.921us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 18.180s 10.300us 0 1 0.00
chip_sw_otp_ctrl_rot_auth_config 7.030s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 157.800s 3548.033us 1 1 100.00
chip_sw_otp_ctrl_descrambling 156.710s 3767.467us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 262.380s 4805.679us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 8.367s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 200.720s 3451.734us 1 1 100.00
ate_bootstrap_flash_erase 599.510s 10010.360us 0 1 0.00
ate_bootstrap_one_frame 6298.710s 44282.282us 1 1 100.00
ate_bootstrap_disjoint 9484.250s 79669.946us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 24 test runs
chip_sw_pwrmgr_sleep_wake_5_bug 19349837449244348093097054083484509775049001604289737362383242719750729822764 None
---- STDERR ----
Another command (pid=2078335) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 9173001118059941000634380290765311158043315123163998156696822826608101501980 None
Another command (pid=377499) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=381681) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=461432) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 73563901679828532985560695068309768931850574777743469243905616920207891647010 None
---- STDERR ----
Another command (pid=473101) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 25204608369529225096233460519636190141331282588672045602012951085362661876063 None
Another command (pid=691287) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=694527) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=698788) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 35375941009060409979620603843876514344700997191570175314042756859444874812139 None
Another command (pid=709520) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=715633) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=715955) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 100284069579709974445690407626208961977013975084922779735221693939795804009990 None
Another command (pid=702268) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=702739) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=704333) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 113647329045206877926717019654697491737472508053537375104299079063651946338328 None
Another command (pid=377499) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=381681) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=461432) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 32123015444097385618825142097827467038525528666628297760432459538473854532030 None
Another command (pid=582226) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=612992) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=613974) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 105461780080408850230858845201764236166494994363817099354672055849582915909138 None
---- STDERR ----
Another command (pid=582226) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 83726579843388546649987240876510596277699403782304694651288618941600687849322 None
Another command (pid=694899) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=694527) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=698788) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 61474651466031328070022961751880376596871466733624660093265304370994628587558 None
Another command (pid=487935) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=643100) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=629266) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 7868948459043654099483491375755660797646705327977247380840281405799221135427 None
---- STDERR ----
Another command (pid=648985) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=646685) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 4487950526472797419731562848080742073482237134623452742112561829104405013490 None
Another command (pid=648985) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=646685) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=603019) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 48230103996576817344260975685475946418006237556900658944490937249416211580902 None
---- STDERR ----
Another command (pid=574258) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 98759776081999650665133262472937794857730253792061016720935704991315615995108 None
Another command (pid=704333) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=673431) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=675811) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 52418939595819082923037258658563679883064773734171251582128305407898772874181 None
Another command (pid=673431) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=675811) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=627046) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 47169156748498488619561290123028236839696021965679157796911929045377221242303 None
Another command (pid=420729) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=462705) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=434214) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 40740128777151982348383678627582968420208923462881840576953138916322000413964 None
Another command (pid=472050) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=469387) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=471581) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 15753451101692912423269757297160374320432401226661628611176331377119911241712 None
Another command (pid=628187) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=585254) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=607795) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 67821180274655828685879026641642548557449445848902499770813943250218027757752 None
---- STDERR ----
Another command (pid=472050) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=469387) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 82732790854614207370490081310763678530565972595636666883528698272165483488192 None
Another command (pid=472050) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=469387) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=483732) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 110374025954889591970243216565142609109039316734251299728099822144038631000872 None
Another command (pid=420729) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=462705) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=388093) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 4277637903296298622468031882047669207563252092335968081847369718996879487967 None
Another command (pid=483732) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=472707) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=566193) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 78875621189136856211545202081201981000712875686741955097343696547859970747292 None
Another command (pid=434214) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=432743) is running. Waiting for it to complete on the server (server_pid=273509)...
Another command (pid=465984) is running. Waiting for it to complete on the server (server_pid=273509)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access 6 test runs
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 85122487020655176601412182462083724065021863914868778493495000735534083094527 333
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 63223235769116865097975919858245581626828480770857689566197242584324296352685 320
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 18200166454707426859366281980027650678767743946418182685638961311636634720236 320
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 992872413735804896459004545122030895199679174342174398613889822011127012984 306
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 107387031598769261735518372384563594772695371381429487349503921279801086877266 304
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 38413000619794081667414196927406959201763549495620194537397318209957569693742 304
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 6 test runs
rom_e2e_sigverify_always_a_bad_b_bad_prod 29688142057828701685898116786977043220553826658292877038949089758297945947089 368
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 109214279688492523474763485171092945808100586142964827198308327769729152217964 365
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 70326726830379466422068975295799326337536860731899442328898508404724175817766 366
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 114498074298994979724846814776624181381431115205038155836648186121421084544158 329
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 96063257981927379597650903212014505705827299772909137666535543359104513931697 329
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 57095672258108472727277882739552338198377953955272051170470674238173874023135 329
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))' 5 test runs
chip_sw_pwrmgr_random_sleep_all_reset_reqs 77070817053499323856678616294667635314039558249071878188191824100305078037779 321
UVM_ERROR @ 6354.790500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6354.790500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 10622786501372172904625970488770430343168214842394267349384636693480315504533 320
UVM_ERROR @ 7012.987000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7012.987000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 96038859654875309186038997519639286902770998820514156044991506954236808194565 331
UVM_ERROR @ 7622.172000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7622.172000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_sysrst_ctrl_reset 37415543061597061564140195902129180757217670808858175284917951822982208454249 340
UVM_ERROR @ 25225.676000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 25225.676000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 28293615796186207738372911664850889520910029975675064129021311400146797769503 325
UVM_ERROR @ 8178.005000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8178.005000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 3 test runs
chip_sw_lc_walkthrough_dev 70507039214734393847998244801844064766501671089218788649592570200514520473098 370
UVM_INFO @ 9334.147925 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 67797409992191074475916342697639325231008502211948392009990852641909512062301 370
UVM_INFO @ 10789.087916 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 36086932186146582712128653880669968976589720915264229567488249324321202959355 342
UVM_INFO @ 7940.980002 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode 3 test runs
rom_e2e_sigverify_always_a_nothing_b_bad_prod 15399057385116589248584350367595573109631581904372024414116613040133376817955 328
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 26566808891613212066434560549679336835290442264213374234659599960308623476566 329
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 48434263775779585945191747445401827227379674884362975108046775726189766684379 329
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))' 2 test runs
chip_sw_pwrmgr_sleep_power_glitch_reset 85208614906452040871088851206782634583148082463065442796677567848946399708484 319
UVM_ERROR @ 4265.731580 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 4265.731580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 9232977506780937248277356669321941443251340071855461402885710001981542340091 347
UVM_ERROR @ 11708.464944 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 11708.464944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 2 test runs
chip_sw_hmac_multistream 36496029177713433416014407009425239233369091273849890301281431874440557405559 363
UVM_INFO @ 12018.537254 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_keymgr_sideload_otbn 15731806427192273552487381955588024307108940977949563183350352599303399222590 340
UVM_INFO @ 20026.686700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *). 2 test runs
chip_tl_errors 64473278316113781988227011902570388605042700073729995933448018514302767320287 224
TL item was: req: (cip_tl_seq_item@106112) { a_addr: 'h10548 a_data: 'hec62fe30 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h25 a_opcode: 'h4 a_user: 'h1ae8f d_param: 'h0 d_source: 'h25 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 4294.236216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 94385676411296200811092137062269538448761155103455714792995303934097728121404 230
TL item was: req: (cip_tl_seq_item@30342) { a_addr: 'h1050c a_data: 'h7858a1f1 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h32 a_opcode: 'h4 a_user: 'h18aae d_param: 'h0 d_source: 'h32 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2542.290589 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 77843191208558731483805856712246163590762790161670408881837076151205185316172 364
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 58921785046109839318118233194725970553701381373233747437403889339569209104782 326
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 2 test runs
rom_e2e_sigverify_always_a_bad_b_bad_dev 20921261020833476117154947286818946686401536611929029000998750548664060001546 366
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 115091885087718349380681500948940978040955745141233619482121130442855893506589 328
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path *rstmgr.u_d0_spi_host*.leaf_rst_path 1 test run
chip_sw_rstmgr_rst_cnsty_escalation 112704051633242347002902086462793324802827160466113886285642440136601296095090 307
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$isunknown(pin_wkup_req_o))' 1 test run
chip_sw_sleep_pin_wake 42142855698542215942469412334104778845994822420630345887260701920272191724438 324
UVM_ERROR @ 3444.759000 us: (pinmux.sv:662) [ASSERT FAILED] AonWkupReqKnownO_A
UVM_INFO @ 3444.759000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty 1 test run
chip_sw_spi_device_pass_through_collision 18289739484439397633273733857647853446325556331696182897413864426175183516681 333
UVM_INFO @ 2839.113892 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_flash_ctrl_lc_rw_en 83230655165447360947039728575955316848839042380814184004660676884119267919013 315
UVM_INFO @ 4292.578110 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * 1 test run
chip_sw_otp_ctrl_lc_signals_rma 107935270779841193195509892223223693258738011314869479481935015290304145268248 348
UVM_INFO @ 10014.461276 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' 1 test run
chip_sw_otp_ctrl_escalation 96095135741769593828835734120698428342159478885954726605978988356351534110960 322
UVM_ERROR @ 3232.004304 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3232.004304 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode 1 test run
chip_sw_otp_ctrl_rot_auth_config 94042020154549901131399721995285527143316349659116504093464023461976128333193 283
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_ctrl_raw_to_scrap 114209611988277063099414503374601741800858308850445451521928279508709767162232 308
UVM_INFO @ 27270.102458 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:945) [chip_sw_lc_volatile_raw_unlock_vseq] Check failed (!(transition_ctrl & (* << *))) VOLATILE_RAW_UNLOCK is not expected to be supported by this top-level. Check the SecVolatileRawUnlockEn parameter configuration. 1 test run
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 18769287948888072661313005551899253657551453997785680544247714943085724358141 315
UVM_INFO @ 3104.365732 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_testunlocks_vseq] max attempt reached to get lc status LcExtClockSwitched! 1 test run
chip_sw_lc_walkthrough_testunlocks 4994096204873781048480745711964531874667915825879103322438961487773302144417 347
UVM_INFO @ 35334.836614 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))' 1 test run
chip_sw_pwrmgr_full_aon_reset 62363763428142108560271564056367714224366633554220330266480771811460448681145 326
UVM_ERROR @ 5665.426964 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A
UVM_INFO @ 5665.426964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns 1 test run
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 23601960570747225723115193327723569140075232690940232089107670753617049559670 338
UVM_INFO @ 35766.813542 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:391)] CHECK-fail: Expect alert *! 1 test run
chip_sw_alert_test 62286208112546372760207198571073655776080424951783656624228972126561027825099 313
UVM_INFO @ 4550.623836 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) 1 test run
chip_sw_alert_handler_lpg_sleep_mode_alerts 84180332777700260773138786044552138903289671371037467428144596026978054600273 309
UVM_INFO @ 2856.688349 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
chip_sw_alert_handler_lpg_sleep_mode_pings 65062295636186545322965198369988780884097194165851668552714075822399952711300 None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected 1 test run
chip_sw_clkmgr_jitter_frequency 34875826116347302950304109061519507218641806271524200163130910966951766721675 349
UVM_INFO @ 4227.041420 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep. 1 test run
chip_sw_rv_dm_access_after_wakeup 98712398925664275996517712656747858049009958884024916258128027371804554092427 335
UVM_INFO @ 14193.192910 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rv_jtag_o == '0)' 1 test run
chip_sw_rv_dm_access_after_escalation_reset 53442177055513581446615476632394993630143573285164064938159124910718620687165 317
UVM_ERROR @ 3481.682982 us: (pinmux_strap_sampling.sv:516) [ASSERT FAILED] RvTapOff1_A
UVM_INFO @ 3481.682982 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch 1 test run
chip_rv_dm_lc_disabled 74770541759301196588783398934154109890154790494090008081992466535512378120633 221
UVM_INFO @ 3252.951966 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_idle_load 111701200852785343860347709851043541961932257394385189717127920755565354834767 324
UVM_INFO @ 15285.594582 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*) 1 test run
chip_sw_power_sleep_load 100562207454993289540838220395696133998451104227127537063499459434008433201437 343
UVM_INFO @ 15537.866751 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = * 1 test run
chip_sw_ast_clk_rst_inputs 48945947075975736742523126811788218563298387783444615854582522551232839479460 333
UVM_INFO @ 11593.012446 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:619) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_*.opcode (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1) 1 test run
ate_bootstrap_flash_erase 9643871545178698548064287632829992907614529040595895951957745713847368107774 273
UVM_INFO @ 10010.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:*-*-* 1 test run
rom_e2e_shutdown_exception_c 39376203166786463751747753247968217813665992490809735306919100481221664221920 320
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 5920.088269 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:*-*-* 1 test run
rom_e2e_shutdown_output 22627680475240613773410034707096519821116521841232766648577628472609793951808 313
" == "OpenTitan:4001-0002-01
"
UVM_INFO @ 10533.303011 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 83202060989545360055736348211563931308370029092231841798723808323229645794861 327
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode 1 test run
rom_e2e_sigverify_always_a_nothing_b_bad_dev 104084971288484521446771121882760332162130316773321991203269542253884306585757 328
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds 1 test run
rom_e2e_jtag_debug_rma 45286397971353853416400403026680051499673614776238755675197935403419113651391 319
UVM_INFO @ 3911.919888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_meas 31005449255998318334762110285623486454548034709550467403505053169195696649472 320
UVM_INFO @ 17138.323941 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns * 1 test run
rom_e2e_keymgr_init_rom_ext_invalid_meas 108699394147472655164567536526413821126275360044238480218493115342009101191442 320
UVM_INFO @ 16611.544776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)' 1 test run
rom_keymgr_functest 10484447415173691426283147588691978852016407631610219131842851667260897274833 333
UVM_ERROR @ 7420.953150 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 7420.953150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---