Simulation Results: clkmgr

 
30/07/2026 15:30:28 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.46 %
  • code
  • 96.78 %
  • assert
  • 92.94 %
  • func
  • 81.65 %
  • line
  • 98.50 %
  • branch
  • 97.75 %
  • cond
  • 88.96 %
  • toggle
  • 98.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
66.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.920s 25.684us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.740s 24.191us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.840s 38.522us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 5.280s 285.506us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.190s 70.763us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.180s 72.111us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.840s 38.522us 1 1 100.00
clkmgr_csr_aliasing 1.190s 70.763us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.660s 14.736us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.120s 37.431us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.730s 22.496us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.700s 21.298us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.920s 25.684us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 2.200s 522.263us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 8.150s 2943.136us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 2.200s 522.263us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 6.940s 2603.465us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.850s 92.165us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.600s 111.949us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.600s 111.949us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.740s 24.191us 1 1 100.00
clkmgr_csr_rw 0.840s 38.522us 1 1 100.00
clkmgr_csr_aliasing 1.190s 70.763us 1 1 100.00
clkmgr_same_csr_outstanding 1.030s 120.691us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.740s 24.191us 1 1 100.00
clkmgr_csr_rw 0.840s 38.522us 1 1 100.00
clkmgr_csr_aliasing 1.190s 70.763us 1 1 100.00
clkmgr_same_csr_outstanding 1.030s 120.691us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 0.670s 2.303us 0 1 0.00
clkmgr_tl_intg_err 23.800s 10265.179us 0 1 0.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 814.020s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 814.020s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 814.020s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 814.020s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 5.930s 2159.295us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 23.800s 10265.179us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 2.200s 522.263us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 8.150s 2943.136us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 814.020s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.940s 50.249us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.910s 78.788us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.030s 117.127us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 1.010s 26.097us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.760s 45.348us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.840s 38.522us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.670s 2.303us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.840s 38.522us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.840s 38.522us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.670s 2.303us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 1.190s 203.642us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 13.910s 2134.116us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 40069755553680034466272308100152296156154677911085158227808245645094219149765 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils_pkg::csr_wr_sub.isolation_fork] Timeout waiting to csr_wr clkmgr_reg_block.jitter_enable (addr=*) 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 1522159444499470049626097643758166695443803103644392735852538636122776552344 76
UVM_INFO @ 2159295101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 76989381355067177392216478042391592916451409573067374298277923667434093014060 78
UVM_INFO @ 2302573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_tl_intg_err 111972703701020533104342641274812165136091782153182397510980945073521714284227 171
UVM_INFO @ 10265178882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---