Simulation Results: csrng

 
30/07/2026 15:30:28 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.19 %
  • code
  • 94.70 %
  • assert
  • 94.54 %
  • func
  • 78.31 %
  • block
  • 96.95 %
  • line
  • 97.76 %
  • branch
  • 92.51 %
  • toggle
  • 93.31 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 21.759us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 16.552us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 19.895us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 17.000s 1159.663us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 7.000s 552.705us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 53.760us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 19.895us 1 1 100.00
csrng_csr_aliasing 7.000s 552.705us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 3.000s 48.570us 1 1 100.00
alerts 1 1 100.00
csrng_alert 9.000s 577.490us 1 1 100.00
err 1 1 100.00
csrng_err 3.000s 155.077us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 3.000s 49.740us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 3.000s 49.740us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 617.000s 53222.673us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 35.256us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 46.860us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 6.000s 135.555us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 6.000s 135.555us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 16.552us 1 1 100.00
csrng_csr_rw 2.000s 19.895us 1 1 100.00
csrng_csr_aliasing 7.000s 552.705us 1 1 100.00
csrng_same_csr_outstanding 3.000s 164.088us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 16.552us 1 1 100.00
csrng_csr_rw 2.000s 19.895us 1 1 100.00
csrng_csr_aliasing 7.000s 552.705us 1 1 100.00
csrng_same_csr_outstanding 3.000s 164.088us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 256.786us 1 1 100.00
csrng_tl_intg_err 4.000s 147.058us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 1.000s 3.771us 0 1 0.00
csrng_csr_rw 2.000s 19.895us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 9.000s 577.490us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 617.000s 53222.673us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 3.000s 48.570us 1 1 100.00
csrng_err 3.000s 155.077us 1 1 100.00
csrng_sec_cm 3.000s 256.786us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 3.000s 48.570us 1 1 100.00
csrng_err 3.000s 155.077us 1 1 100.00
csrng_sec_cm 3.000s 256.786us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 3.000s 48.570us 1 1 100.00
csrng_err 3.000s 155.077us 1 1 100.00
csrng_sec_cm 3.000s 256.786us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 3.000s 48.570us 1 1 100.00
csrng_err 3.000s 155.077us 1 1 100.00
csrng_sec_cm 3.000s 256.786us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 3.000s 48.570us 1 1 100.00
csrng_err 3.000s 155.077us 1 1 100.00
csrng_sec_cm 3.000s 256.786us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 9.000s 577.490us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 3.000s 48.570us 1 1 100.00
csrng_err 3.000s 155.077us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 617.000s 53222.673us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 9.000s 577.490us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 147.058us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 3.000s 48.570us 1 1 100.00
csrng_err 3.000s 155.077us 1 1 100.00
csrng_sec_cm 3.000s 256.786us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 3.000s 48.570us 1 1 100.00
csrng_err 3.000s 155.077us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 3.000s 48.570us 1 1 100.00
csrng_err 3.000s 155.077us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 3.000s 48.570us 1 1 100.00
csrng_err 3.000s 155.077us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 3.000s 48.570us 1 1 100.00
csrng_err 3.000s 155.077us 1 1 100.00
csrng_sec_cm 3.000s 256.786us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 3.000s 48.570us 1 1 100.00
csrng_err 3.000s 155.077us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3602.176s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 1 test run
csrng_regwen 56822001441802537703516371852773693385804349864454121699770344815457273099744 99
UVM_INFO @ 3771190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 82696262149214367087416169138880636751946923157999725442006371345220718823488 None