Simulation Results: edn/edn0

 
30/07/2026 15:30:28 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.40 %
  • code
  • 80.81 %
  • assert
  • 95.44 %
  • func
  • 79.96 %
  • line
  • 97.23 %
  • branch
  • 90.38 %
  • cond
  • 85.26 %
  • toggle
  • 81.74 %
  • FSM
  • 49.46 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.830s 31.475us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.980s 45.510us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.980s 50.142us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.660s 661.168us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.570s 40.312us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.060s 32.287us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.980s 50.142us 1 1 100.00
edn_csr_aliasing 1.570s 40.312us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.290s 72.966us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.290s 72.966us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.290s 72.966us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.810s 29.107us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.980s 22.788us 1 1 100.00
errs 1 1 100.00
edn_err 0.980s 33.156us 1 1 100.00
disable 2 2 100.00
edn_disable 1.070s 14.404us 1 1 100.00
edn_disable_auto_req_mode 1.000s 51.486us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.450s 136.836us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.870s 189.285us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.990s 62.687us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.190s 533.100us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.190s 533.100us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.980s 45.510us 1 1 100.00
edn_csr_rw 0.980s 50.142us 1 1 100.00
edn_csr_aliasing 1.570s 40.312us 1 1 100.00
edn_same_csr_outstanding 1.280s 34.763us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.980s 45.510us 1 1 100.00
edn_csr_rw 0.980s 50.142us 1 1 100.00
edn_csr_aliasing 1.570s 40.312us 1 1 100.00
edn_same_csr_outstanding 1.280s 34.763us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.860s 913.395us 1 1 100.00
edn_tl_intg_err 1.290s 94.640us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.000s 20.759us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.980s 22.788us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.860s 913.395us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.860s 913.395us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.860s 913.395us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.860s 913.395us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.980s 22.788us 1 1 100.00
edn_sec_cm 6.860s 913.395us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.980s 22.788us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.290s 94.640us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 43.270s 4727.910us 1 1 100.00