Simulation Results: edn/edn1

 
30/07/2026 15:30:28 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.05 %
  • code
  • 84.18 %
  • assert
  • 97.14 %
  • func
  • 79.83 %
  • line
  • 98.18 %
  • branch
  • 93.29 %
  • cond
  • 89.69 %
  • toggle
  • 94.29 %
  • FSM
  • 45.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.910s 25.639us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.770s 49.397us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.750s 43.975us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.300s 543.170us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.040s 27.596us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.430s 37.922us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.750s 43.975us 1 1 100.00
edn_csr_aliasing 1.040s 27.596us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.280s 103.073us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.280s 103.073us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.280s 103.073us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.990s 22.077us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.030s 255.050us 1 1 100.00
errs 1 1 100.00
edn_err 1.070s 70.768us 1 1 100.00
disable 2 2 100.00
edn_disable 0.770s 12.261us 1 1 100.00
edn_disable_auto_req_mode 0.850s 103.916us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.050s 1136.753us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.890s 47.856us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.790s 15.294us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.030s 60.778us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.030s 60.778us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.770s 49.397us 1 1 100.00
edn_csr_rw 0.750s 43.975us 1 1 100.00
edn_csr_aliasing 1.040s 27.596us 1 1 100.00
edn_same_csr_outstanding 0.950s 32.360us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.770s 49.397us 1 1 100.00
edn_csr_rw 0.750s 43.975us 1 1 100.00
edn_csr_aliasing 1.040s 27.596us 1 1 100.00
edn_same_csr_outstanding 0.950s 32.360us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.000s 566.489us 1 1 100.00
edn_tl_intg_err 1.300s 326.803us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.770s 40.128us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.030s 255.050us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.000s 566.489us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.000s 566.489us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.000s 566.489us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.000s 566.489us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.030s 255.050us 1 1 100.00
edn_sec_cm 2.000s 566.489us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.030s 255.050us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.300s 326.803us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 54.780s 14768.367us 1 1 100.00