| V1 |
|
100.00% |
| V2 |
|
98.28% |
| V2S |
|
91.67% |
| V3 |
|
100.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| flash_ctrl_smoke | 41.740s | 32.032us | 1 | 1 | 100.00 | |
| smoke_hw | 1 | 1 | 100.00 | |||
| flash_ctrl_smoke_hw | 9.450s | 20.020us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_hw_reset | 14.120s | 36.581us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 8.480s | 57.219us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_bit_bash | 52.770s | 4157.202us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_aliasing | 30.580s | 1695.447us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_mem_rw_with_rand_reset | 10.790s | 96.251us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| flash_ctrl_csr_rw | 8.480s | 57.219us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_aliasing | 30.580s | 1695.447us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| flash_ctrl_mem_walk | 5.370s | 16.636us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| flash_ctrl_mem_partial_access | 5.530s | 62.094us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| sw_op | 1 | 1 | 100.00 | |||
| flash_ctrl_sw_op | 11.290s | 24.161us | 1 | 1 | 100.00 | |
| host_read_direct | 1 | 1 | 100.00 | |||
| flash_ctrl_host_dir_rd | 49.170s | 175.064us | 1 | 1 | 100.00 | |
| rma_hw_if | 3 | 3 | 100.00 | |||
| flash_ctrl_hw_rma | 1157.310s | 342593.932us | 1 | 1 | 100.00 | |
| flash_ctrl_hw_rma_reset | 509.100s | 40131.149us | 1 | 1 | 100.00 | |
| flash_ctrl_lcmgr_intg | 5.570s | 149.376us | 1 | 1 | 100.00 | |
| host_controller_arb | 1 | 1 | 100.00 | |||
| flash_ctrl_host_ctrl_arb | 1412.210s | 254491.666us | 1 | 1 | 100.00 | |
| erase_suspend | 1 | 1 | 100.00 | |||
| flash_ctrl_erase_suspend | 136.610s | 1324.477us | 1 | 1 | 100.00 | |
| program_reset | 1 | 1 | 100.00 | |||
| flash_ctrl_prog_reset | 5.560s | 42.234us | 1 | 1 | 100.00 | |
| full_memory_access | 1 | 1 | 100.00 | |||
| flash_ctrl_full_mem_access | 1668.500s | 223606.200us | 1 | 1 | 100.00 | |
| rd_buff_eviction | 1 | 1 | 100.00 | |||
| flash_ctrl_rd_buff_evict | 36.180s | 149.338us | 1 | 1 | 100.00 | |
| rd_buff_eviction_w_ecc | 3 | 3 | 100.00 | |||
| flash_ctrl_rw_evict | 14.270s | 340.067us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_evict_all_en | 12.540s | 84.689us | 1 | 1 | 100.00 | |
| flash_ctrl_re_evict | 14.870s | 99.383us | 1 | 1 | 100.00 | |
| host_arb | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_arb | 48.780s | 155.138us | 1 | 1 | 100.00 | |
| host_interleave | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_arb | 48.780s | 155.138us | 1 | 1 | 100.00 | |
| memory_protection | 1 | 1 | 100.00 | |||
| flash_ctrl_mp_regions | 271.280s | 12934.613us | 1 | 1 | 100.00 | |
| fetch_code | 1 | 1 | 100.00 | |||
| flash_ctrl_fetch_code | 13.330s | 1433.982us | 1 | 1 | 100.00 | |
| all_partitions | 1 | 1 | 100.00 | |||
| flash_ctrl_rand_ops | 93.950s | 318.452us | 1 | 1 | 100.00 | |
| error_mp | 1 | 1 | 100.00 | |||
| flash_ctrl_error_mp | 643.950s | 8390.318us | 1 | 1 | 100.00 | |
| error_prog_win | 1 | 1 | 100.00 | |||
| flash_ctrl_error_prog_win | 342.530s | 3890.771us | 1 | 1 | 100.00 | |
| error_prog_type | 1 | 1 | 100.00 | |||
| flash_ctrl_error_prog_type | 989.810s | 995.773us | 1 | 1 | 100.00 | |
| error_read_seed | 1 | 1 | 100.00 | |||
| flash_ctrl_hw_read_seed_err | 6.040s | 23.044us | 1 | 1 | 100.00 | |
| read_write_overflow | 1 | 1 | 100.00 | |||
| flash_ctrl_oversize_error | 120.000s | 29904.757us | 1 | 1 | 100.00 | |
| flash_ctrl_disable | 1 | 1 | 100.00 | |||
| flash_ctrl_disable | 11.040s | 32.523us | 1 | 1 | 100.00 | |
| flash_ctrl_connect | 1 | 1 | 100.00 | |||
| flash_ctrl_connect | 8.520s | 87.802us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| flash_ctrl_stress_all | 372.720s | 265.365us | 1 | 1 | 100.00 | |
| secret_partition | 2 | 2 | 100.00 | |||
| flash_ctrl_hw_sec_otp | 37.870s | 4601.527us | 1 | 1 | 100.00 | |
| flash_ctrl_otp_reset | 54.460s | 144.315us | 1 | 1 | 100.00 | |
| isolation_partition | 1 | 1 | 100.00 | |||
| flash_ctrl_hw_rma | 1157.310s | 342593.932us | 1 | 1 | 100.00 | |
| interrupts | 4 | 4 | 100.00 | |||
| flash_ctrl_intr_rd | 150.850s | 2052.706us | 1 | 1 | 100.00 | |
| flash_ctrl_intr_wr | 44.500s | 10204.044us | 1 | 1 | 100.00 | |
| flash_ctrl_intr_rd_slow_flash | 72.990s | 6231.445us | 1 | 1 | 100.00 | |
| flash_ctrl_intr_wr_slow_flash | 106.090s | 27044.112us | 1 | 1 | 100.00 | |
| invalid_op | 1 | 1 | 100.00 | |||
| flash_ctrl_invalid_op | 35.440s | 4143.999us | 1 | 1 | 100.00 | |
| mid_op_rst | 1 | 1 | 100.00 | |||
| flash_ctrl_mid_op_rst | 30.890s | 1001.446us | 1 | 1 | 100.00 | |
| double_bit_err | 5 | 5 | 100.00 | |||
| flash_ctrl_read_word_sweep_derr | 10.190s | 537.957us | 1 | 1 | 100.00 | |
| flash_ctrl_ro_derr | 76.430s | 660.606us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_derr | 119.010s | 6827.822us | 1 | 1 | 100.00 | |
| flash_ctrl_derr_detect | 93.680s | 2314.519us | 1 | 1 | 100.00 | |
| flash_ctrl_integrity | 292.820s | 16768.095us | 1 | 1 | 100.00 | |
| single_bit_err | 2 | 3 | 66.67 | |||
| flash_ctrl_read_word_sweep_serr | 10.200s | 29.752us | 1 | 1 | 100.00 | |
| flash_ctrl_ro_serr | 73.060s | 2634.898us | 1 | 1 | 100.00 | |
| flash_ctrl_rw_serr | 3603.503s | 0.000us | 0 | 1 | 0.00 | |
| singlebit_err_counter | 1 | 1 | 100.00 | |||
| flash_ctrl_serr_counter | 34.720s | 2692.032us | 1 | 1 | 100.00 | |
| singlebit_err_address | 1 | 1 | 100.00 | |||
| flash_ctrl_serr_address | 42.460s | 4553.329us | 1 | 1 | 100.00 | |
| scramble | 5 | 5 | 100.00 | |||
| flash_ctrl_wo | 89.810s | 2982.544us | 1 | 1 | 100.00 | |
| flash_ctrl_write_word_sweep | 6.370s | 44.962us | 1 | 1 | 100.00 | |
| flash_ctrl_read_word_sweep | 5.960s | 54.683us | 1 | 1 | 100.00 | |
| flash_ctrl_ro | 74.780s | 2456.149us | 1 | 1 | 100.00 | |
| flash_ctrl_rw | 332.880s | 20346.407us | 1 | 1 | 100.00 | |
| filesystem_support | 1 | 1 | 100.00 | |||
| flash_ctrl_fs_sup | 21.700s | 383.842us | 1 | 1 | 100.00 | |
| rma_write_process_error | 2 | 2 | 100.00 | |||
| flash_ctrl_rma_err | 523.140s | 103282.246us | 1 | 1 | 100.00 | |
| flash_ctrl_hw_prog_rma_wipe_err | 62.070s | 10020.410us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| flash_ctrl_alert_test | 6.700s | 194.165us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| flash_ctrl_intr_test | 5.580s | 19.129us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_errors | 7.010s | 85.895us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_errors | 7.010s | 85.895us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| flash_ctrl_csr_hw_reset | 14.120s | 36.581us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_rw | 8.480s | 57.219us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_aliasing | 30.580s | 1695.447us | 1 | 1 | 100.00 | |
| flash_ctrl_same_csr_outstanding | 10.290s | 2918.746us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| flash_ctrl_csr_hw_reset | 14.120s | 36.581us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_rw | 8.480s | 57.219us | 1 | 1 | 100.00 | |
| flash_ctrl_csr_aliasing | 30.580s | 1695.447us | 1 | 1 | 100.00 | |
| flash_ctrl_same_csr_outstanding | 10.290s | 2918.746us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 38.260s | 373.028us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 38.260s | 373.028us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 38.260s | 373.028us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 38.260s | 373.028us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors_with_csr_rw | 24.910s | 300.866us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| flash_ctrl_sec_cm | 1741.070s | 5676.078us | 1 | 1 | 100.00 | |
| flash_ctrl_tl_intg_err | 380.560s | 821.732us | 1 | 1 | 100.00 | |
| sec_cm_reg_bus_integrity | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_intg_err | 380.560s | 821.732us | 1 | 1 | 100.00 | |
| sec_cm_host_bus_integrity | 1 | 1 | 100.00 | |||
| flash_ctrl_tl_intg_err | 380.560s | 821.732us | 1 | 1 | 100.00 | |
| sec_cm_mem_bus_integrity | 2 | 2 | 100.00 | |||
| flash_ctrl_rd_intg | 13.170s | 180.604us | 1 | 1 | 100.00 | |
| flash_ctrl_wr_intg | 6.350s | 52.740us | 1 | 1 | 100.00 | |
| sec_cm_scramble_key_sideload | 1 | 1 | 100.00 | |||
| flash_ctrl_smoke | 41.740s | 32.032us | 1 | 1 | 100.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 4 | 4 | 100.00 | |||
| flash_ctrl_otp_reset | 54.460s | 144.315us | 1 | 1 | 100.00 | |
| flash_ctrl_disable | 11.040s | 32.523us | 1 | 1 | 100.00 | |
| flash_ctrl_sec_info_access | 35.180s | 2593.032us | 1 | 1 | 100.00 | |
| flash_ctrl_connect | 8.520s | 87.802us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_config_regwen | 6.800s | 189.827us | 1 | 1 | 100.00 | |
| sec_cm_data_regions_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 8.480s | 57.219us | 1 | 1 | 100.00 | |
| sec_cm_data_regions_config_shadow | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 38.260s | 373.028us | 1 | 1 | 100.00 | |
| sec_cm_info_regions_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 8.480s | 57.219us | 1 | 1 | 100.00 | |
| sec_cm_info_regions_config_shadow | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 38.260s | 373.028us | 1 | 1 | 100.00 | |
| sec_cm_bank_config_regwen | 1 | 1 | 100.00 | |||
| flash_ctrl_csr_rw | 8.480s | 57.219us | 1 | 1 | 100.00 | |
| sec_cm_bank_config_shadow | 1 | 1 | 100.00 | |||
| flash_ctrl_shadow_reg_errors | 38.260s | 373.028us | 1 | 1 | 100.00 | |
| sec_cm_mem_ctrl_global_esc | 1 | 1 | 100.00 | |||
| flash_ctrl_disable | 11.040s | 32.523us | 1 | 1 | 100.00 | |
| sec_cm_mem_ctrl_local_esc | 2 | 2 | 100.00 | |||
| flash_ctrl_rd_intg | 13.170s | 180.604us | 1 | 1 | 100.00 | |
| flash_ctrl_access_after_disable | 6.360s | 75.725us | 1 | 1 | 100.00 | |
| sec_cm_mem_addr_infection | 1 | 1 | 100.00 | |||
| flash_ctrl_host_addr_infection | 14.680s | 92.833us | 1 | 1 | 100.00 | |
| sec_cm_mem_disable_config_mubi | 1 | 1 | 100.00 | |||
| flash_ctrl_disable | 11.040s | 32.523us | 1 | 1 | 100.00 | |
| sec_cm_exec_config_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_fetch_code | 13.330s | 1433.982us | 1 | 1 | 100.00 | |
| sec_cm_mem_scramble | 1 | 1 | 100.00 | |||
| flash_ctrl_rw | 332.880s | 20346.407us | 1 | 1 | 100.00 | |
| sec_cm_mem_integrity | 2 | 3 | 66.67 | |||
| flash_ctrl_rw_serr | 3603.503s | 0.000us | 0 | 1 | 0.00 | |
| flash_ctrl_rw_derr | 119.010s | 6827.822us | 1 | 1 | 100.00 | |
| flash_ctrl_integrity | 292.820s | 16768.095us | 1 | 1 | 100.00 | |
| sec_cm_rma_entry_mem_sec_wipe | 1 | 1 | 100.00 | |||
| flash_ctrl_hw_rma | 1157.310s | 342593.932us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1741.070s | 5676.078us | 1 | 1 | 100.00 | |
| sec_cm_phy_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1741.070s | 5676.078us | 1 | 1 | 100.00 | |
| sec_cm_phy_prog_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1741.070s | 5676.078us | 1 | 1 | 100.00 | |
| sec_cm_ctr_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1741.070s | 5676.078us | 1 | 1 | 100.00 | |
| sec_cm_phy_arbiter_ctrl_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_arb_redun | 6.740s | 959.753us | 1 | 1 | 100.00 | |
| sec_cm_phy_host_grant_ctrl_consistency | 0 | 1 | 0.00 | |||
| flash_ctrl_phy_host_grant_err | 5.630s | 5.970us | 0 | 1 | 0.00 | |
| sec_cm_phy_ack_ctrl_consistency | 1 | 1 | 100.00 | |||
| flash_ctrl_phy_ack_consistency | 5.730s | 24.760us | 1 | 1 | 100.00 | |
| sec_cm_fifo_ctr_redun | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1741.070s | 5676.078us | 1 | 1 | 100.00 | |
| sec_cm_mem_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1741.070s | 5676.078us | 1 | 1 | 100.00 | |
| sec_cm_prog_tl_lc_gate_fsm_sparse | 1 | 1 | 100.00 | |||
| flash_ctrl_sec_cm | 1741.070s | 5676.078us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| asymmetric_read_path | 1 | 1 | 100.00 | |||
| flash_ctrl_rd_ooo | 19.990s | 679.089us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| flash_ctrl_basic_rw | 187.990s | 5029.775us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job timed out after * minutes | 1 test run | |||
| flash_ctrl_rw_serr | 114647278126862135072513103679668640372909154257973294403496460510198852238659 | None | ||
| Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))' | 1 test run | |||
| flash_ctrl_phy_host_grant_err | 74682246532955750983683489641496938501221787742089963159582113394011787747777 | 130 |
UVM_ERROR @ 5969.6 ns: (alert_esc_if.sv:211) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 5969.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|