Simulation Results: hmac

 
30/07/2026 15:30:28 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.13 %
  • code
  • 97.12 %
  • assert
  • 97.60 %
  • func
  • 42.67 %
  • line
  • 99.69 %
  • branch
  • 99.01 %
  • cond
  • 95.73 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 10.490s 1513.856us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.860s 44.061us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.820s 62.214us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 6.930s 308.044us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.330s 211.813us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.290s 21.823us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.820s 62.214us 1 1 100.00
hmac_csr_aliasing 3.330s 211.813us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 16.790s 7553.625us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 30.080s 1121.057us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 7.700s 236.351us 1 1 100.00
hmac_test_sha384_vectors 19.580s 778.012us 1 1 100.00
hmac_test_sha512_vectors 443.290s 49122.989us 1 1 100.00
hmac_test_hmac256_vectors 5.630s 241.420us 1 1 100.00
hmac_test_hmac384_vectors 10.150s 1864.429us 1 1 100.00
hmac_test_hmac512_vectors 10.270s 450.748us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 16.790s 4084.050us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 352.370s 4544.252us 1 1 100.00
error 1 1 100.00
hmac_error 4.300s 559.386us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 37.040s 21330.089us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 10.490s 1513.856us 1 1 100.00
hmac_long_msg 16.790s 7553.625us 1 1 100.00
hmac_back_pressure 30.080s 1121.057us 1 1 100.00
hmac_datapath_stress 352.370s 4544.252us 1 1 100.00
hmac_burst_wr 16.790s 4084.050us 1 1 100.00
hmac_stress_all 652.300s 212716.952us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 10.490s 1513.856us 1 1 100.00
hmac_long_msg 16.790s 7553.625us 1 1 100.00
hmac_back_pressure 30.080s 1121.057us 1 1 100.00
hmac_datapath_stress 352.370s 4544.252us 1 1 100.00
hmac_wipe_secret 37.040s 21330.089us 1 1 100.00
hmac_test_sha256_vectors 7.700s 236.351us 1 1 100.00
hmac_test_sha384_vectors 19.580s 778.012us 1 1 100.00
hmac_test_sha512_vectors 443.290s 49122.989us 1 1 100.00
hmac_test_hmac256_vectors 5.630s 241.420us 1 1 100.00
hmac_test_hmac384_vectors 10.150s 1864.429us 1 1 100.00
hmac_test_hmac512_vectors 10.270s 450.748us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 10.490s 1513.856us 1 1 100.00
hmac_long_msg 16.790s 7553.625us 1 1 100.00
hmac_back_pressure 30.080s 1121.057us 1 1 100.00
hmac_datapath_stress 352.370s 4544.252us 1 1 100.00
hmac_burst_wr 16.790s 4084.050us 1 1 100.00
hmac_error 4.300s 559.386us 1 1 100.00
hmac_wipe_secret 37.040s 21330.089us 1 1 100.00
hmac_test_sha256_vectors 7.700s 236.351us 1 1 100.00
hmac_test_sha384_vectors 19.580s 778.012us 1 1 100.00
hmac_test_sha512_vectors 443.290s 49122.989us 1 1 100.00
hmac_test_hmac256_vectors 5.630s 241.420us 1 1 100.00
hmac_test_hmac384_vectors 10.150s 1864.429us 1 1 100.00
hmac_test_hmac512_vectors 10.270s 450.748us 1 1 100.00
hmac_stress_all 652.300s 212716.952us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 652.300s 212716.952us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.550s 30.070us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.580s 29.337us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.030s 66.245us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.030s 66.245us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.860s 44.061us 1 1 100.00
hmac_csr_rw 0.820s 62.214us 1 1 100.00
hmac_csr_aliasing 3.330s 211.813us 1 1 100.00
hmac_same_csr_outstanding 1.760s 157.284us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.860s 44.061us 1 1 100.00
hmac_csr_rw 0.820s 62.214us 1 1 100.00
hmac_csr_aliasing 3.330s 211.813us 1 1 100.00
hmac_same_csr_outstanding 1.760s 157.284us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.730s 45.597us 1 1 100.00
hmac_tl_intg_err 1.440s 384.088us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.440s 384.088us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 10.490s 1513.856us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.210s 1835.128us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 86.450s 8453.169us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.760s 10.404us 1 1 100.00