Simulation Results

Simulation Results: i2c

30/07/2026 15:30:28 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.35 %

code
78.35 %

assert
97.46 %

func
80.23 %

line
96.38 %

branch
92.26 %

cond
85.04 %

toggle
74.04 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	19.530s	8561.555us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	17.860s	4323.168us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.720s	27.658us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.620s	17.208us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	2.070s	1310.366us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.260s	79.506us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.120s	110.679us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.620s	17.208us	1	1	100.00
	i2c_csr_aliasing	1.260s	79.506us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.670s	21.098us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	80.040s	12157.365us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	27.730s	28388.943us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.620s	92.498us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	80.020s	11045.085us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	31.700s	2266.948us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.780s	172.172us	1	1	100.00
	i2c_host_fifo_fmt_empty	3.170s	339.277us	1	1	100.00
	i2c_host_fifo_reset_rx	5.590s	192.991us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	44.920s	2804.392us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	16.820s	634.847us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.490s	80.505us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	1.700s	2749.423us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	207.030s	30820.275us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	2.380s	540.241us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	7.350s	858.036us	1	1	100.00
	i2c_target_intr_smoke	5.460s	5768.126us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	0.870s	480.274us	1	1	100.00
	i2c_target_fifo_reset_tx	0.890s	582.739us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	132.900s	44986.696us	1	1	100.00
	i2c_target_stress_rd	7.350s	858.036us	1	1	100.00
	i2c_target_intr_stress_wr	81.750s	21060.076us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	3.950s	1401.101us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	10.910s	1213.062us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	2.930s	972.613us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	2.350s	11550.362us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.450s	2661.511us	1	1	100.00
	i2c_target_fifo_watermarks_tx	0.960s	332.755us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	27.730s	28388.943us	1	1	100.00
	i2c_host_perf_precise	1.060s	142.163us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	16.820s	634.847us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	1.210s	74.313us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	1.720s	1952.125us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.570s	541.914us	1	1	100.00
	i2c_target_nack_txstretch	1.150s	520.119us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	8.510s	1743.211us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.270s	838.874us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.660s	39.636us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.640s	29.760us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	0.980s	52.575us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	0.980s	52.575us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.720s	27.658us	1	1	100.00
	i2c_csr_rw	0.620s	17.208us	1	1	100.00
	i2c_csr_aliasing	1.260s	79.506us	1	1	100.00
	i2c_same_csr_outstanding	0.790s	174.243us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.720s	27.658us	1	1	100.00
	i2c_csr_rw	0.620s	17.208us	1	1	100.00
	i2c_csr_aliasing	1.260s	79.506us	1	1	100.00
	i2c_same_csr_outstanding	0.790s	174.243us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.140s	71.762us	1	1	100.00
	i2c_sec_cm	0.850s	66.213us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.140s	71.762us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	1.680s	212.545us	1
target_error_intr				1
	i2c_target_unexp_stop	0.970s	136.719us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	3.000s	182.580us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	92093596436891445563117446806297431883755212788317755559890488001632560961320	85	UVM_INFO @ 21098467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	19423716233943739429661491306284006455507244812492740272918557266227519683070	98	UVM_INFO @ 12157364677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	61874293055363394368414888514841821701920737056910589467919131542162190718760	84	UVM_INFO @ 212545440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	85980950605107588090667582347174738820935851895179679368271742356635468856087	83	UVM_INFO @ 182580451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	113309460851467425530364001750575846591466968906086854119693641039039149257490	89	UVM_INFO @ 2749423257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	107380456291246639554007254596522311674397800846515188589057678120101554346522	83	UVM_INFO @ 136718874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	72314044737766043561174924193726984326189258146978131329309453046392736111394	84	UVM_INFO @ 11550362242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:				1 test run
	i2c_host_mode_toggle	11259291990040681560708978329737482419812559734793841954194231837287403824162	85	---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @22935