Simulation Results: keymgr

 
30/07/2026 15:30:28 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.43 %
  • code
  • 92.56 %
  • assert
  • 97.49 %
  • func
  • 48.23 %
  • line
  • 98.72 %
  • branch
  • 97.81 %
  • cond
  • 92.64 %
  • toggle
  • 87.58 %
  • FSM
  • 86.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 1.340s 137.904us 1 1 100.00
random 1 1 100.00
keymgr_random 2.360s 1055.226us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 0.880s 64.082us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 0.820s 35.959us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 4.290s 193.262us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 4.740s 271.988us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.080s 71.711us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 0.820s 35.959us 1 1 100.00
keymgr_csr_aliasing 4.740s 271.988us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 1.770s 50.944us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 1.580s 131.561us 1 1 100.00
keymgr_sideload_kmac 1.760s 48.420us 1 1 100.00
keymgr_sideload_aes 1.970s 1430.329us 1 1 100.00
keymgr_sideload_otbn 1.800s 295.917us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 1.580s 292.769us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 1.490s 135.893us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 1.850s 159.415us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 1.920s 95.054us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 1.350s 34.673us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.150s 133.391us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 3.940s 151.817us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.630s 36.774us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.650s 14.390us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.090s 24.814us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.090s 24.814us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 0.880s 64.082us 1 1 100.00
keymgr_csr_rw 0.820s 35.959us 1 1 100.00
keymgr_csr_aliasing 4.740s 271.988us 1 1 100.00
keymgr_same_csr_outstanding 1.880s 270.525us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 0.880s 64.082us 1 1 100.00
keymgr_csr_rw 0.820s 35.959us 1 1 100.00
keymgr_csr_aliasing 4.740s 271.988us 1 1 100.00
keymgr_same_csr_outstanding 1.880s 270.525us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 6.410s 1091.284us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 6.410s 1091.284us 1 1 100.00
keymgr_tl_intg_err 4.560s 1593.706us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.330s 944.242us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.330s 944.242us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.330s 944.242us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.330s 944.242us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 4.460s 275.860us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 6.410s 1091.284us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 6.410s 1091.284us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 4.560s 1593.706us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.330s 944.242us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 1.770s 50.944us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 2.360s 1055.226us 1 1 100.00
keymgr_csr_rw 0.820s 35.959us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 2.360s 1055.226us 1 1 100.00
keymgr_csr_rw 0.820s 35.959us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 2.360s 1055.226us 1 1 100.00
keymgr_csr_rw 0.820s 35.959us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 1.490s 135.893us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.350s 34.673us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 1.350s 34.673us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 2.360s 1055.226us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 1.420s 34.109us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 6.410s 1091.284us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 6.410s 1091.284us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 6.410s 1091.284us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 2.490s 250.253us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 1.490s 135.893us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 6.410s 1091.284us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 6.410s 1091.284us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 6.410s 1091.284us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.490s 250.253us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.490s 250.253us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 6.410s 1091.284us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.490s 250.253us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 6.410s 1091.284us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 2.490s 250.253us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 7.040s 771.626us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
keymgr_stress_all_with_rand_reset 90179217311498981236098545304711890463417959641595607714006859284051520605919 1256
UVM_INFO @ 771625957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---