Simulation Results: lc_ctrl/volatile_unlock_disabled

 
30/07/2026 15:30:28 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.69 %
  • code
  • 83.72 %
  • assert
  • 94.13 %
  • func
  • 91.22 %
  • line
  • 97.28 %
  • branch
  • 93.85 %
  • cond
  • 79.29 %
  • toggle
  • 86.48 %
  • FSM
  • 61.68 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.290s 219.653us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.730s 49.441us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.720s 16.267us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.530s 117.237us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 43.525us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.860s 26.584us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.720s 16.267us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 43.525us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.230s 69.460us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.020s 685.739us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.710s 29.237us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.370s 402.210us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.020s 335.846us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 3.330s 1342.941us 1 1 100.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 7.020s 335.846us 1 1 100.00
lc_ctrl_prog_failure 1.370s 402.210us 1 1 100.00
lc_ctrl_errors 3.330s 1342.941us 1 1 100.00
lc_ctrl_security_escalation 3.840s 663.504us 1 1 100.00
lc_ctrl_jtag_state_failure 15.700s 10086.008us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.520s 71.546us 1 1 100.00
lc_ctrl_jtag_errors 11.250s 25732.262us 0 1 0.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 3.510s 1829.079us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.910s 827.443us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.520s 71.546us 1 1 100.00
lc_ctrl_jtag_errors 11.250s 25732.262us 0 1 0.00
lc_ctrl_jtag_access 2.340s 1094.045us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.380s 1415.432us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.150s 222.426us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.950s 55.927us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.660s 3468.857us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.390s 2110.287us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.900s 32.330us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.030s 240.029us 1 1 100.00
lc_ctrl_jtag_alert_test 1.100s 367.369us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 1.700s 2466.663us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.660s 13.017us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 92.170s 46289.492us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.800s 73.685us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.250s 28.186us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.250s 28.186us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.730s 49.441us 1 1 100.00
lc_ctrl_csr_rw 0.720s 16.267us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 43.525us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.940s 211.277us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.730s 49.441us 1 1 100.00
lc_ctrl_csr_rw 0.720s 16.267us 1 1 100.00
lc_ctrl_csr_aliasing 1.090s 43.525us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.940s 211.277us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.780s 227.996us 1 1 100.00
lc_ctrl_tl_intg_err 1.800s 127.121us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.800s 127.121us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.020s 685.739us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.020s 335.846us 1 1 100.00
lc_ctrl_sec_cm 5.780s 227.996us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.020s 335.846us 1 1 100.00
lc_ctrl_sec_cm 5.780s 227.996us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.020s 335.846us 1 1 100.00
lc_ctrl_sec_cm 5.780s 227.996us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.020s 335.846us 1 1 100.00
lc_ctrl_sec_cm 5.780s 227.996us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.020s 335.846us 1 1 100.00
lc_ctrl_sec_cm 5.780s 227.996us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.020s 335.846us 1 1 100.00
lc_ctrl_sec_cm 5.780s 227.996us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.020s 335.846us 1 1 100.00
lc_ctrl_sec_cm 5.780s 227.996us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.020s 335.846us 1 1 100.00
lc_ctrl_sec_cm 5.780s 227.996us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.840s 663.504us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.230s 69.460us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.910s 827.443us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.430s 322.140us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.430s 322.140us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 3.920s 1094.171us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.220s 3575.963us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.220s 3575.963us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 26.270s 3209.797us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 1 test run
lc_ctrl_jtag_errors 55382320168734319669557796774968698177205289979289973478782341855269035312161 2208
UVM_INFO @ 25732262274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 19766355584427868066570663661547151197413737675514714856724281662858261299464 7170
UVM_INFO @ 3209797065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---