Simulation Results: lc_ctrl/volatile_unlock_enabled

 
30/07/2026 15:30:28 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.42 %
  • code
  • 84.27 %
  • assert
  • 94.69 %
  • func
  • 92.29 %
  • line
  • 97.22 %
  • branch
  • 93.66 %
  • cond
  • 79.47 %
  • toggle
  • 85.57 %
  • FSM
  • 65.42 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 0.940s 72.022us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.710s 30.565us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.740s 19.547us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 0.980s 43.992us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.990s 110.827us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.300s 110.365us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.740s 19.547us 1 1 100.00
lc_ctrl_csr_aliasing 0.990s 110.827us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 1.720s 137.271us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.730s 297.093us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.710s 54.823us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.250s 46.514us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.090s 1886.883us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.080s 1700.695us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.090s 1886.883us 1 1 100.00
lc_ctrl_prog_failure 1.250s 46.514us 1 1 100.00
lc_ctrl_errors 6.080s 1700.695us 1 1 100.00
lc_ctrl_security_escalation 3.880s 298.370us 1 1 100.00
lc_ctrl_jtag_state_failure 13.050s 3509.938us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.460s 1428.298us 1 1 100.00
lc_ctrl_jtag_errors 24.990s 3250.924us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.200s 387.301us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.380s 2014.242us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.460s 1428.298us 1 1 100.00
lc_ctrl_jtag_errors 24.990s 3250.924us 1 1 100.00
lc_ctrl_jtag_access 1.120s 137.403us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.160s 3637.650us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.480s 158.166us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.970s 144.057us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 5.720s 1006.874us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.290s 1149.303us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.880s 124.856us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.350s 577.506us 1 1 100.00
lc_ctrl_jtag_alert_test 1.090s 189.612us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 1.760s 1043.851us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.730s 68.746us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 23.590s 10220.742us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.760s 71.406us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.760s 597.932us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.760s 597.932us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.710s 30.565us 1 1 100.00
lc_ctrl_csr_rw 0.740s 19.547us 1 1 100.00
lc_ctrl_csr_aliasing 0.990s 110.827us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.040s 54.434us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.710s 30.565us 1 1 100.00
lc_ctrl_csr_rw 0.740s 19.547us 1 1 100.00
lc_ctrl_csr_aliasing 0.990s 110.827us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.040s 54.434us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 4.930s 279.909us 1 1 100.00
lc_ctrl_tl_intg_err 1.550s 88.178us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.550s 88.178us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.730s 297.093us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.090s 1886.883us 1 1 100.00
lc_ctrl_sec_cm 4.930s 279.909us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.090s 1886.883us 1 1 100.00
lc_ctrl_sec_cm 4.930s 279.909us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.090s 1886.883us 1 1 100.00
lc_ctrl_sec_cm 4.930s 279.909us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.090s 1886.883us 1 1 100.00
lc_ctrl_sec_cm 4.930s 279.909us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.090s 1886.883us 1 1 100.00
lc_ctrl_sec_cm 4.930s 279.909us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.090s 1886.883us 1 1 100.00
lc_ctrl_sec_cm 4.930s 279.909us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.090s 1886.883us 1 1 100.00
lc_ctrl_sec_cm 4.930s 279.909us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.090s 1886.883us 1 1 100.00
lc_ctrl_sec_cm 4.930s 279.909us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.880s 298.370us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 1.720s 137.271us 1 1 100.00
lc_ctrl_jtag_state_post_trans 7.380s 2014.242us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 3.880s 557.950us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 3.880s 557.950us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.390s 1113.543us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.410s 3799.104us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 3.410s 3799.104us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 29.720s 2439.927us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 108736558626751175070173621927443954933392823161178835845930650625219034415012 3638
UVM_INFO @ 2439926677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---