Simulation Results: otbn

 
30/07/2026 15:30:28 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.75 %
  • code
  • 81.89 %
  • assert
  • 89.49 %
  • func
  • 97.88 %
  • block
  • 97.72 %
  • line
  • 97.93 %
  • branch
  • 81.71 %
  • toggle
  • 81.71 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 67.205us 1 1 100.00
single_binary 1 1 100.00
otbn_single 10.000s 68.108us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 19.000s 15.262us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 20.000s 28.206us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 24.000s 149.116us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 21.000s 38.670us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 21.000s 67.961us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 20.000s 28.206us 1 1 100.00
otbn_csr_aliasing 21.000s 38.670us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 50.000s 11157.251us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 28.000s 641.490us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 33.000s 345.030us 1 1 100.00
multi_error 0 1 0.00
otbn_multi_err 28.000s 72.748us 0 1 0.00
back_to_back 1 1 100.00
otbn_multi 56.000s 227.216us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 90.000s 1741.487us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 14.000s 155.850us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 11.128us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 7.000s 13.317us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 25.000s 47.373us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 13.000s 57.498us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 190.772us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 190.772us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 19.000s 15.262us 1 1 100.00
otbn_csr_rw 20.000s 28.206us 1 1 100.00
otbn_csr_aliasing 21.000s 38.670us 1 1 100.00
otbn_same_csr_outstanding 4.000s 22.410us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 19.000s 15.262us 1 1 100.00
otbn_csr_rw 20.000s 28.206us 1 1 100.00
otbn_csr_aliasing 21.000s 38.670us 1 1 100.00
otbn_same_csr_outstanding 4.000s 22.410us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 18.000s 25.255us 1 1 100.00
otbn_dmem_err 16.000s 21.508us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 28.000s 84.441us 1 1 100.00
otbn_controller_ispr_rdata_err 27.000s 231.984us 1 1 100.00
otbn_mac_bignum_acc_err 15.000s 181.310us 1 1 100.00
otbn_urnd_err 5.000s 27.793us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 19.000s 47.784us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 14.000s 39.887us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 12.000s 14.987us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 167.000s 871.643us 1 1 100.00
otbn_tl_intg_err 18.000s 1526.187us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 27.000s 167.014us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 167.000s 871.643us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 167.000s 871.643us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 67.205us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 16.000s 21.508us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 18.000s 25.255us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 18.000s 1526.187us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 14.000s 155.850us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 18.000s 25.255us 1 1 100.00
otbn_dmem_err 16.000s 21.508us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 11.128us 1 1 100.00
otbn_illegal_mem_acc 19.000s 47.784us 1 1 100.00
otbn_sec_cm 167.000s 871.643us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 167.000s 871.643us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 10.000s 68.108us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 18.000s 25.255us 1 1 100.00
otbn_dmem_err 16.000s 21.508us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 11.128us 1 1 100.00
otbn_illegal_mem_acc 19.000s 47.784us 1 1 100.00
otbn_sec_cm 167.000s 871.643us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 167.000s 871.643us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 14.000s 155.850us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 18.000s 25.255us 1 1 100.00
otbn_dmem_err 16.000s 21.508us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 11.128us 1 1 100.00
otbn_illegal_mem_acc 19.000s 47.784us 1 1 100.00
otbn_sec_cm 167.000s 871.643us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 167.000s 871.643us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 10.000s 68.108us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 17.000s 13.961us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 8.000s 48.899us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 19.000s 338.086us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 19.000s 338.086us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 8.000s 84.269us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 167.000s 871.643us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 167.000s 871.643us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 10.000s 56.168us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 167.000s 871.643us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 167.000s 871.643us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 16.000s 513.175us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 16.000s 513.175us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 6.000s 49.032us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 10.000s 68.108us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 10.000s 68.108us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 10.000s 68.108us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 56.000s 227.216us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 10.000s 68.108us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 10.000s 68.108us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 10.000s 81.115us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 10.000s 68.108us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 167.000s 871.643us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 240.000s 9344.111us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 35.977us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_multi_err 44007004700831413608224502300626978760809378370400068047679664198676596479650 291
UVM_INFO @ 72748266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:377) [csr_utils_pkg::csr_rd_sub.isolation_fork] Timeout waiting to csr_rd otbn_reg_block.err_bits (addr=*) 1 test run
otbn_stress_all_with_rand_reset 59017398946533320150491964091090337794213068740860621870566320944782609105821 540
UVM_INFO @ 9344111430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---