Simulation Results: otp_ctrl

 
30/07/2026 15:30:28 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.16 %
  • code
  • 77.91 %
  • assert
  • 94.64 %
  • func
  • 73.93 %
  • line
  • 88.43 %
  • branch
  • 83.26 %
  • cond
  • 90.24 %
  • toggle
  • 83.70 %
  • FSM
  • 43.92 %
Validation stages
V1
100.00%
V2
95.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.360s 113.438us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.610s 525.340us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.020s 206.412us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.530s 170.402us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.650s 5249.425us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.250s 60.855us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.220s 112.677us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.530s 170.402us 1 1 100.00
otp_ctrl_csr_aliasing 2.250s 60.855us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.070s 75.219us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.040s 536.710us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 14.020s 3402.408us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.460s 142.802us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 15.130s 1650.285us 1 1 100.00
otp_ctrl_check_fail 1.900s 90.919us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 2.480s 218.956us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 9.470s 2684.560us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 3.310s 540.396us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 7.270s 976.891us 1 1 100.00
otp_ctrl_parallel_lc_esc 2.850s 1510.171us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 11.560s 929.950us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 12.330s 3527.464us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 11.410s 1168.497us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 124.630s 35208.755us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.090s 40.164us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.790s 601.435us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 2.520s 202.475us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 2.520s 202.475us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.020s 206.412us 1 1 100.00
otp_ctrl_csr_rw 1.530s 170.402us 1 1 100.00
otp_ctrl_csr_aliasing 2.250s 60.855us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.340s 176.796us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.020s 206.412us 1 1 100.00
otp_ctrl_csr_rw 1.530s 170.402us 1 1 100.00
otp_ctrl_csr_aliasing 2.250s 60.855us 1 1 100.00
otp_ctrl_same_csr_outstanding 1.340s 176.796us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
otp_ctrl_tl_intg_err 13.250s 4609.986us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 13.250s 4609.986us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.610s 525.340us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.610s 525.340us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.850s 1510.171us 1 1 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.850s 1510.171us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.850s 1510.171us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.850s 1510.171us 1 1 100.00
otp_ctrl_macro_errs 12.330s 3527.464us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.850s 1510.171us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.850s 1510.171us 1 1 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.850s 1510.171us 1 1 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.850s 1510.171us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.850s 1510.171us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.850s 1510.171us 1 1 100.00
otp_ctrl_macro_errs 12.330s 3527.464us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 2.850s 1510.171us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 2.850s 1510.171us 1 1 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.460s 142.802us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 1.900s 90.919us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 9.470s 2684.560us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 9.470s 2684.560us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 9.470s 2684.560us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 9.470s 2684.560us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 9.470s 2684.560us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.610s 525.340us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 9.470s 2684.560us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.610s 525.340us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.740s 157330.977us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 2.480s 218.956us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.610s 525.340us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.610s 525.340us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 12.330s 3527.464us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 8.740s 8017.755us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 51.930s 10801.954us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1208) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 2 test runs
otp_ctrl_check_fail 3664335317799353598371880891814505767981672191704512627781459587457333860256 699
UVM_INFO @ 90918535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all_with_rand_reset 62960713679857574237880561042302761882996941710918065880290837662798250232836 9241
UVM_INFO @ 10801953950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---