Simulation Results: pwrmgr

 
30/07/2026 15:30:28 DVSim: v1.50.0 sha: 2695753 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.95 %
  • code
  • 97.40 %
  • assert
  • 98.43 %
  • func
  • 98.02 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 95.90 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
86.67%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.600s 30.285us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.630s 26.456us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.590s 38.014us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.350s 209.732us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.820s 61.363us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.800s 55.979us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.590s 38.014us 1 1 100.00
pwrmgr_csr_aliasing 0.820s 61.363us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.610s 55.537us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.610s 55.537us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.710s 224.139us 1 1 100.00
pwrmgr_lowpower_invalid 0.660s 38.815us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 1.210s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 0.750s 114.275us 1 1 100.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 1.210s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.850s 298.419us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.700s 213.174us 1 1 100.00
disable_rom_integrity_check 0 1 0.00
pwrmgr_disable_rom_integrity_check 1.870s 1000.000us 0 1 0.00
stress_all 1 1 100.00
pwrmgr_stress_all 0.910s 407.995us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.600s 50.110us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.400s 163.171us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.400s 163.171us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.630s 26.456us 1 1 100.00
pwrmgr_csr_rw 0.590s 38.014us 1 1 100.00
pwrmgr_csr_aliasing 0.820s 61.363us 1 1 100.00
pwrmgr_same_csr_outstanding 0.820s 42.685us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.630s 26.456us 1 1 100.00
pwrmgr_csr_rw 0.590s 38.014us 1 1 100.00
pwrmgr_csr_aliasing 0.820s 61.363us 1 1 100.00
pwrmgr_same_csr_outstanding 0.820s 42.685us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 1.170s 249.690us 1 1 100.00
pwrmgr_sec_cm 0.980s 365.752us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 0.980s 365.752us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 0.980s 365.752us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 1.170s 249.690us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.020s 786.511us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.850s 298.419us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.540s 861.273us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.720s 260.013us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.610s 29.769us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 0.980s 365.752us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 0.980s 365.752us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 0.980s 365.752us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.580s 35.642us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.590s 62.774us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.620s 56.748us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.590s 38.014us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.590s 38.014us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.750s 102.853us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 1.160s 193.216us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 2 test runs
pwrmgr_reset 104039262815587023275219547807582616928991500154975587406962038240055687952616 127
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_disable_rom_integrity_check 50046581770846424621222322950594312802777424708950536817551472343845258221960 184
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---